AD9228BCPZRL7-65 Analog Devices Inc, AD9228BCPZRL7-65 Datasheet - Page 29

• Manufacturer Part Number: AD9228BCPZRL7-65
• Description: IC,A/D CONVERTER,QUAD,12-BIT,LLCC,48PIN
• Manufacturer: Analog Devices Inc

Specifications of AD9228BCPZRL7-65

• Number Of Bits: 12
• Sampling Rate (per Second): 65M
• Data Interface: Serial, SPI™
• Number Of Converters: 4
• Power Dissipation (max): 510mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9228-65EBZ - BOARD EVAL FOR AD9228
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SCLK/DTP Pin
The SCLK/DTP pin is for use in applications that do not require
SPI mode operation. This pin can enable a single digital test
pattern if it and the CSB pin are held high during device power-
up. When SCLK/DTP is tied to AVDD, the ADC channel
outputs shift out the following pattern: 1000 0000 0000. The
FCO and DCO function normally while all channels shift out the
repeatable test pattern. This pattern allows the user to perform
timing alignment adjustments among the FCO, DCO, and output
data. For normal operation, this pin should be tied to AGND
through a 10 k Ω resistor. This pin is both 1.8 V and 3.3 V tolerant.
Table 12. Digital Test Pattern Pin Settings
Selected DTP
Normal
DTP
Additional and custom test patterns can also be observed when
commanded from the SPI port. Consult the Memory Map
section for information about the options available.
CSB Pin
The CSB pin should be tied to AVDD for applications that do
not require SPI mode operation. By tying CSB high, all SCLK
and SDIO information is ignored. This pin is both 1.8 V and
3.3 V tolerant.
Operation
DTP Voltage
10 kΩ to AGND
AVDD
Resulting
D + x and D − x
Normal
operation
1000 0000 0000
Resulting
FCO and DCO
Normal operation
Normal operation
Rev. D | Page 29 of 56
RBIAS Pin
To set the internal core bias current of the ADC, place a resistor
(nominally equal to 10.0 kΩ) to ground at the RBIAS pin. The
resistor current is derived on-chip and sets the AVDD current of
the ADC to a nominal 232 mA at 65 MSPS. Therefore, it is
imperative that at least a 1% tolerance on this resistor be used to
achieve consistent performance.
Voltage Reference
A stable, accurate 0.5 V voltage reference is built into the
AD9228. It is gained up internally by a factor of 2, setting V
to 1.0 V, which results in a full-scale differential input span of
2 V p-p. The V
pin can be driven externally with a 1.0 V reference to improve
accuracy.
When applying the decoupling capacitors to the VREF, REFT,
and REFB pins, use ceramic low ESR capacitors. These capacitors
should be close to the ADC pins and on the same layer of the
PCB as the AD9228. The recommended capacitor values and
configurations for the AD9228 reference pin are shown in
Figure 64.
Table 13. Reference Settings
Selected Mode
External
Internal,
Reference
2 V p-p FSR
REF
SENSE Voltage
AVDD
AGND to 0.2 V
is set internally by default; however, the VREF
Resulting VREF (V)
N/A
1.0
AD9228
Resulting
Differential
Span (V p-p)
2 × external
reference
2.0
REF