AD9229BCPZ-50 Analog Devices Inc, AD9229BCPZ-50 Datasheet - Page 18

• Manufacturer Part Number: AD9229BCPZ-50
• Description: IC,A/D CONVERTER,QUAD,12-BIT,CMOS,LLCC,48PIN
• Manufacturer: Analog Devices Inc

Specifications of AD9229BCPZ-50

• Number Of Bits: 12
• Sampling Rate (per Second): 50M
• Data Interface: Serial
• Number Of Converters: 4
• Power Dissipation (max): 1.08W
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9229-65EBZ - BOARD EVALUATION FOR AD9229
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9229
THEORY OF OPERATION
The AD9229 architecture consists of a front-end switched capa-
citor sample-and-hold amplifier (SHA) followed by a pipelined
ADC. The pipelined ADC is divided into three sections: a 4-bit
first stage followed by eight 1.5-bit stages and a final 3-bit flash.
Each stage provides sufficient overlap to correct for flash errors
in the preceding stages. The quantized outputs from each stage
are combined into a final 12-bit result in the digital correction
logic. The pipelined architecture permits the first stage to
operate on a new input sample while the remaining stages
operate on preceding samples. Sampling occurs on the rising
edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched capacitor DAC
and interstage residue amplifier (MDAC). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage simply consists of a flash ADC.
The input stage contains a differential SHA that can be config-
ured as ac- or dc-coupled in differential or single-ended modes.
The output staging block aligns the data, carries out the error
correction, and passes the data to the output buffers. The data is
then serialized and aligned to the frame and output clock.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9229 is a differential switched-
capacitor SHA that has been designed for optimum perfor-
mance while processing a differential input signal. The SHA
input can support a wide common-mode range and maintain
excellent performance. An input common-mode voltage of
midsupply minimizes signal-dependent errors and provides
optimum performance.
The clock signal alternately switches the SHA between sample
mode and hold mode (see Figure 34). When the SHA is
switched into sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half
VIN+
VIN–
C
C
PAR
PAR
Figure 34. Switched-Capacitor SHA Input
S
S
S
S
H
H
Rev. B | Page 18 of 40
of a clock cycle. A small resistor in series with each input can
help reduce the peak transient current required from the output
stage of the driving source. Also, a small shunt capacitor can
be placed across the inputs to provide dynamic charging
currents. This passive network creates a low-pass filter at the
ADC’s input; therefore, the precise values are dependent on
the application.
The analog inputs of the AD9229 are not internally dc-biased.
In ac-coupled applications, the user must provide this bias
externally. For optimum performance, set the device so that
V
range with reasonable performance (see Figure 35 and Figure 36).
For best dynamic performance, the source impedances driving
VIN+ and VIN− should be matched such that common-mode
settling errors are symmetrical. These errors are reduced by the
common-mode rejection of the ADC.
CM
= AVDD/2; however, the device can function over a wider
Figure 35. SNR/SFDR vs. Common-Mode Voltage, f
Figure 36. SNR/SFDR vs. Common-Mode Voltage, f
90
85
80
75
70
65
60
90
85
80
75
70
65
60
55
50
45
40
0
0
ANALOG INPUT COMMON-MODE VOLTAGE (V)
ANALOG INPUT COMMON-MODE VOLTAGE (V)
0.5
0.5
2V p-p, SNR (dB)
1V p-p, SNR (dB)
2V p-p, SFDR (dBc)
2V p-p, SNR (dB)
1V p-p, SNR (dB)
1V p-p, SFDR (dBc)
f
f
1.0
1.0
SAMPLE
SAMPLE
1V p-p, SFDR (dBc)
= 65 MSPS
= 65 MSPS
1.5
1.5
2V p-p, SFDR (dBc)
2.0
2.0
IN
IN
2.5
2.5
= 2.4 MHz,
= 30 MHz,
3.0
3.0