AD9229BCPZ-50 Analog Devices Inc, AD9229BCPZ-50 Datasheet - Page 21

• Manufacturer Part Number: AD9229BCPZ-50
• Description: IC,A/D CONVERTER,QUAD,12-BIT,CMOS,LLCC,48PIN
• Manufacturer: Analog Devices Inc

Specifications of AD9229BCPZ-50

• Number Of Bits: 12
• Sampling Rate (per Second): 50M
• Data Interface: Serial
• Number Of Converters: 4
• Power Dissipation (max): 1.08W
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9229-65EBZ - BOARD EVALUATION FOR AD9229
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The AD9229’s LVDS outputs facilitate interfacing with LVDS
receivers in custom ASICs and FPGAs that have LVDS capa-
bility for superior switching performance in noisy environ-
ments. Single point-to-point net topologies are recommended
with a 100 Ω termination resistor placed as close to the receiver
as possible. It is recommended to keep the trace length no
longer than 12 inches and to keep differential output traces
close together and at equal lengths.
The format of the output data is offset binary. An example of
the output coding format can be found in Table 8.
Table 8. Digital Output Coding
Code
4095
2048
2047
0
Timing
Data from each ADC is serialized and provided on a separate
channel. The data rate for each serial stream is equal to 12 bits
times the sample clock rate, with a maximum of 780 bps (12 bits
× 65 MSPS = 780 bps). The lowest typical conversion rate is
10 MSPS.
Two output clocks are provided to assist in capturing data from
the AD9229. The DCO is used to clock the output data and is
equal to six times the sampling clock (CLK) rate. Data is
clocked out of the AD9229 and can be captured on the rising
and falling edges of the DCO that supports double-data rate
(DDR) capturing. The frame clock out (FCO) is used to signal
the start of a new output byte and is equal to the sampling clock
rate. See the timing diagram shown in Figure 2 for more
information.
DTP Pin
The digital test pattern (DTP) pin can be enabled for two types
of test patterns, as summarized in Table 9. When the DTP is
tied to AVDD/3, all the ADC channel outputs shift out the
following pattern: 1000 0000 0000. When the DTP is tied to 2 ×
AVDD/3, all the ADC channel outputs shift out the following
pattern: 1010 1010 1010. The FCO and DCO outputs still work
as usual while all channels shift out the test pattern. This
pattern allows the user to perform timing alignment
adjustments between the FCO, DCO, and the output data. For
normal operation, this pin should be tied to AGND.
(VIN+) − (VIN−),
Input Span =
2 V p-p (V)
1.000
0
−0.000488
−1.00
(VIN+) − (VIN−),
Input Span =
1 V p-p (V)
0.500
0
−0.000244
−0.5000
Digital Output
Offset Binary
(D11 ... D0)
1111 1111 1111
1000 0000 0000
0111 1111 1111
0000 0000 0000
Rev. B | Page 21 of 40
Table 9. Digital Test Pattern Pin Settings
Selected DTP
Normal
operation
DTP1
DTP2
Restricted
Voltage Reference
A stable and accurate 0.5 V voltage reference is built into the
AD9229. The input range can be adjusted by varying the refer-
ence voltage applied to the AD9229, using either the internal
reference or an externally applied reference voltage. The input
span of the ADC tracks reference voltage changes linearly.
When applying the decoupling capacitors to the VREF, REFT,
and REFB pins, use ceramic, low ESR capacitors. These
capacitors should be close to the ADC pins and on the same
layer of the PCB as the AD9229. The recommended capacitor
values and configurations for the AD9229 reference pin can be
found in Figure 42 and Figure 43.
Table 10. Reference Settings
Selected Mode
External Reference
Internal, 1 V p-p FSR
Programmable
Internal, 2 V p-p FSR
Internal Reference Connection
A comparator within the AD9229 detects the potential at the
SENSE pin and configures the reference into four possible states
(summarized in Table 10). If SENSE is grounded, the reference
amplifier switch is connected to the internal resistor divider (see
Figure 42), setting VREF to 1 V. Connecting the SENSE pin to
the VREF pin switches the amplifier output to the SENSE pin,
configuring the internal op amp circuit as a voltage follower and
providing a 0.5 V reference output. If an external resistor
divider is connected as shown in Figure 43, the switch is again
set to the SENSE pin. This puts the reference amplifier in a
noninverting mode and defines the VREF output as
In all reference configurations, REFT and REFB establish their
input span of the ADC core. The analog input full-scale range
of the ADC equals twice the voltage at the reference pin for
either an internal or an external reference configuration.
VREF
=
0
5 .
×
AGND
AVDD/3
2 × AVDD/3
AVDD
DTP Voltage
⎛ +
⎜
⎝
1
SENSE
Voltage
AVDD
VREF
0.2 V to
VREF
AGND to
0.2 V
R2
R1
⎞
⎟
⎠
1000 0000 0000
1010 1010 1010
Resulting
D+ and D–
Normal
operation
N/A
Resulting
VREF (V)
N/A
0.5
0.5 × (1 +
R2/R1)
1.0
Resulting
FCO and DCO
Normal
operation
Normal
operation
Normal
operation
N/A
Resulting
Differential
Span (V p-p)
2 × external
reference
1.0
2 × VREF
2.0
AD9229