AD9229BCPZRL7-65 Analog Devices Inc, AD9229BCPZRL7-65 Datasheet - Page 19

• Manufacturer Part Number: AD9229BCPZRL7-65
• Description: IC,A/D CONVERTER,QUAD,12-BIT,CMOS,LLCC,48PIN
• Manufacturer: Analog Devices Inc

Specifications of AD9229BCPZRL7-65

• Number Of Bits: 12
• Sampling Rate (per Second): 65M
• Data Interface: Serial
• Number Of Converters: 4
• Power Dissipation (max): 1.47W
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9229-65EBZ - BOARD EVALUATION FOR AD9229
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

An internal reference buffer creates the positive and negative
reference voltages, REFT and REFB, respectively, that defines
the span of the ADC core. The output common-mode of the
reference buffer is set to midsupply, and the REFT and REFB
voltages and span are defined as
It can be seen from the equations above that the REFT and
REFB voltages are symmetrical about the midsupply voltage
and, by definition, the input span is twice the value of the
VREF voltage.
The internal voltage reference can be pin-strapped to fixed
values of 0.5 V or 1.0 V or adjusted within the same range, as
discussed in the Internal Reference Connection section.
Maximum SNR performance is achieved by setting the AD9229
to the largest input span of 2 V p-p.
The SHA should be driven from a source that keeps the signal
peaks within the allowable range for the selected reference
voltage. The minimum and maximum common-mode input
levels are defined in Figure 35 and Figure 36.
Differential Input Configurations
Optimum performance is achieved by driving the AD9229 in a
differential input configuration. For ultrasound applications,
the AD8332 differential driver provides excellent performance
and a flexible interface to the ADC (see Figure 37).
1V p-p
However, the noise performance of most amplifiers is not
adequate to achieve the true performance of the AD9229. For
applications where SNR is a key parameter, differential transfor-
mer coupling is the recommended input configuration. An
example of this is shown in Figure 38.
In any configuration, the value of the shunt capacitor, C, is
dependent on the input frequency and may need to be reduced
or removed.
REFT = 1/2 (AVDD + VREF)
REFB = 1/2 (AVDD − VREF)
Span = 2 × (REFT − REFB) = 2 × VREF
0.1μF
Figure 37. Differential Input Configuration Using the AD8332
120nH
0.1μF
22p
18nF
INH
LMD
274Ω
LNA
LON
LOP
0.1μF
0.1μF
AD8332
VIP
VIN
VGA
VOH
VOL
187nH
187Ω
374Ω
0.1μF
0.1μF
1.0kΩ
1.0kΩ
0.1μF
R
R
C
10μF
VIN+
VIN–
VREF
AD9229
AGND
AVDD
AVDD
Rev. B | Page 19 of 40
Single-Ended Input Configuration
A single-ended input can provide adequate performance in
cost-sensitive applications. In this configuration, SFDR and
distortion performance degrade due to the large input
common-mode swing. However, if the source impedances
on each input are matched, there should be little effect on
SNR performance. Figure 39 details a typical single-ended
input configuration.
CLOCK INPUT CONSIDERATIONS
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals and, as a result, may be sensi-
tive to clock duty cycle. Typically, a 10% tolerance is required on
the clock duty cycle to maintain dynamic performance charac-
teristics. The AD9229 has a self-contained clock duty cycle
stabilizer that retimes the nonsampling edge, providing an
internal clock signal with a nominal 50% duty cycle. This allows
a wide range of clock input duty cycles without affecting the
performance of the AD9229.
An on-board phase-locked loop (PLL) multiplies the input
clock rate for the purpose of shifting the serial data out. The
stability criteria for the PLL limits the minimum sample clock
rate of the ADC to 10 MSPS. Assuming steady state operation of
the input clock, any sudden change in the sampling rate could
create an out-of-lock condition leading to invalid outputs at the
DCO, FCO, and data out pins.
2V p-p
2V p-p
Figure 38. Differential Transformer—Coupled Configuration
10μF
49.9Ω
1kΩ
1kΩ
Figure 39. Single-Ended Input Configuration
AVDD
49.9Ω
10μF
0.1μF
0.1μF
0.1μF
AVDD
1kΩ
1kΩ
1kΩ
1kΩ
R
R
R
C
R
C
VIN+
VIN–
AD9229
VIN+
VIN–
AGND
AVDD
AD9229
AGND
AVDD
AD9229