AD9230-250EBZ Analog Devices Inc, AD9230-250EBZ Datasheet - Page 25

• Manufacturer Part Number: AD9230-250EBZ
• Description: 12-Bit 250 Msps ADC EB
• Manufacturer: Analog Devices Inc

Specifications of AD9230-250EBZ

• Number Of Adc's: 1
• Number Of Bits: 12
• Sampling Rate (per Second): 250M
• Data Interface: Serial
• Inputs Per Adc: 1 Single Ended
• Input Range: 1.0 ~ 1.5 V
• Power (typ) @ Conditions: 434mW @ 250MSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9230
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 9. Serial Port Pins
Mnemonic
SCLK
SDIO
CSB
RESET
The falling edge of the CSB, in conjunction with the rising edge
of the SCLK, determines the start of the framing. An example of
the serial timing and its definitions can be found in Figure 64
and Table 11.
During an instruction phase, a 16-bit instruction is transmitted.
Data then follows the instruction phase and is determined by
the W0 and W1 bits, which is 1 or more bytes of data. All data is
composed of 8-bit words. The first bit of each individual byte of
serial data indicates whether this is a read or write command.
This allows the serial data input/output (SDIO) pin to change
direction from an input to an output.
Data may be sent in MSB or in LSB first mode. MSB first is
default on power-up and can be changed by changing the
configuration register. For more information about this feature
and others, see Interfacing to High Speed ADCs via SPI at
www.analog.com.
SCLK
SDIO
CSB
DON’T CARE
DON’T CARE
Function
SCLK (Serial Clock) is the serial shift clock in.
SCLK is used to synchronize serial interface
reads and writes.
SDIO (Serial Data Input/Output) is a dual-purpose
pin. The typical role for this pin is an input and
output depending on the instruction being sent
and the relative position in the timing frame.
CSB (Chip Select Bar) is active low controls that
gates the read and write cycles.
Master Device Reset. When asserted, device
assumes default settings. Active low.
t
S
R/W
t
DS
W1
W0
t
DH
A12
A11
t
HI
Figure 64. Serial Port Interface Timing Diagram
A10
t
LO
A9
Rev. 0 | Page 25 of 32
t
CLK
A8
A7
HARDWARE INTERFACE
The pins described in Table 9 comprise the physical interface
between the user’s programming device and the serial port of
the AD9230. All serial pins are inputs, which is an open-drain
output and should be tied to an external pull-up or pull-down
resistor (suggested value of 10 kΩ).
This interface is flexible enough to be controlled by either
PROMS or PIC mirocontrollers as well. This provides the user
with an alternate method to program the ADC other than a SPI
controller.
If the user chooses not to use the SPI interface, some pins serve
a dual function and are associated with a specific function when
strapped externally to AVDD or ground during device power
on. The Configuration Without the SPI section describes the
strappable functions supported on the AD9230.
CONFIGURATION WITHOUT THE SPI
In applications that do not interface to the SPI control registers,
the SPI SDIO/DCS and SPI SCLK/DFS pins can alternately
serve as standalone CMOS-compatible control pins. When the
device is powered up, it is assumed that the user intends to use
the pins as static control lines for the duty cycle stabilizer. In
this mode, the SPI CSB chip select should be connected to
ground, which disables the serial port interface.
Table 10. Mode Selection
Mnemonic
SPI SDIO/DCS
SPI SCLK/DFS
D5
D4
External
Voltage
AVDD
AGND
AVDD
AGND
D3
D2
Configuration
Duty cycle stabilizer enabled
Duty cycle stabilizer disabled
Twos complement enabled
Offset binary enabled
D1
D0
t
H
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AD9230
DON’T CARE