AD9255-105EBZ Analog Devices Inc, AD9255-105EBZ Datasheet - Page 33
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AD9255-105EBZ
Manufacturer Part Number
AD9255-105EBZ
Description
14 Bit 105 Msps High SNR 1.8V ADC
Manufacturer
Analog Devices Inc
Datasheet
1.AD9255BCPZRL7-80.pdf
(44 pages)
Specifications of AD9255-105EBZ
Number Of Adc's
1
Number Of Bits
14
Sampling Rate (per Second)
105M
Data Interface
Serial, SPI™
Inputs Per Adc
1 Differential
Input Range
1 ~ 2 Vpp
Power (typ) @ Conditions
371mW @ 125MSPS
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Utilized Ic / Part
AD9255
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST
The AD9255 includes built-in self-test features designed to
enable verification of the integrity of the part as well as facilitate
board level debugging. A built-in self-test (BIST) feature is included
that verifies the integrity of the digital datapath of the AD9255.
Various output test options are also provided to place predictable
values on the outputs of the AD9255.
BUILT-IN SELF-TEST (BIST)
The BIST is a thorough test of the digital portion of the selected
AD9255 signal path. When enabled, the test runs from an internal
pseudorandom noise (PN) source through the digital datapath
starting at the ADC block output. The BIST sequence runs for
512 cycles and stops. The BIST signature value is placed in
Register 0x24 and Register 0x25.
The outputs are not disconnected during this test, so the PN
sequence can be observed as it runs. The PN sequence can be
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continued from its last value or reset from the beginning, based
on the value programmed in Register 0x0E, Bit 2. The BIST
signature result varies based on the part configuration.
OUTPUT TEST MODES
The output test options are shown in Table 17. When an output
test mode is enabled, the analog section of the ADC is discon-
nected from the digital back end blocks and the test pattern is run
through the output formatting block. Some of the test patterns are
subject to output formatting, and some are not. The seed value for
the PN sequence tests can be forced if the PN reset bits are used
to hold the generator in reset mode by setting Bit 4 or Bit 5 of
Register 0x0D. These tests can be performed with or without
an analog signal (if present, the analog signal is ignored), but
they do require an encode clock. For more information, see
AN-877 Application Note, Interfacing to High Speed ADCs via SPI.
AD9255