AD9266BCPZRL7-65 Analog Devices Inc, AD9266BCPZRL7-65 Datasheet - Page 21

• Manufacturer Part Number: AD9266BCPZRL7-65
• Description: 16 Bit, 65 MSPS 1.8V Single ADC
• Manufacturer: Analog Devices Inc

Specifications of AD9266BCPZRL7-65

• Number Of Bits: 16
• Sampling Rate (per Second): 65M
• Data Interface: Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 113mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Input Clock Divider
The AD9266 contains an input clock divider with the ability
to divide the input clock by integer values between 1 and 8.
Optimum performance can be obtained by enabling the internal
duty cycle stabilizer (DCS) when using divide ratios other than
1, 2, or 4.
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate
a variety of internal timing signals and, as a result, may be
sensitive to clock duty cycle. Commonly, a ±5% tolerance is
required on the clock duty cycle to maintain dynamic
performance characteristics.
The AD9266 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling (falling) edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows the user to
provide a wide range of clock input duty cycles without affecting
the performance of the AD9266. Noise and distortion perform-
ance are nearly flat for a wide range of duty cycles with the DCS on,
as shown in Figure 51.
Jitter in the rising edge of the input is still of concern and is not
easily reduced by the internal stabilization circuit. The duty
cycle control loop does not function for clock rates less than
20 MHz nominally. The loop has a time constant associated
with it that must be considered in applications in which the
clock rate can change dynamically. A wait time of 1.5 μs to 5 μs
is required after a dynamic clock frequency increase or decrease
before the DCS loop is relocked to the input signal.
80
79
78
77
76
75
74
73
72
71
70
30
35
Figure 51. SNR vs. DCS On/Off
40
POSITIVE DUTY CYCLE (%)
45
50
55
60
DCS OFF
DCS ON
65
70
Rev. 0 | Page 21 of 32
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR from the low frequency
SNR (SNR
(t
In the previous equation, the rms aperture jitter represents the
clock input jitter specification. IF undersampling applications
are particularly sensitive to jitter, as illustrated in Figure 52.
The clock input should be treated as an analog signal when
aperture jitter may affect the dynamic range of the AD9266. To
avoid modulating the clock signal with digital noise, keep power
supplies for clock drivers separate from the ADC output driver
supplies. Low jitter, crystal-controlled oscillators make the best
clock sources. If the clock is generated from another type of source
(by gating, dividing, or another method), it should be retimed by
the original clock at the last step.
For more information, see the AN-501 Application Note and
the AN-756 Application Note available at www.analog.com.
JRMS
SNR
) can be calculated by
80
75
70
65
60
55
50
45
1
HF
LF
= −10 log[(2π × f
) at a given input frequency (f
Figure 52. SNR vs. Input Frequency and Jitter
10
FREQUENCY (MHz)
INPUT
× t
JRMS
)
100
2
INPUT
+ 10
3.0ps
) due to jitter
(
−
SNR
0.05ps
0.2ps
0.5ps
1.0ps
1.5ps
2.0ps
2.5ps
LF
AD9266
/
10
)
1k
]