AD9272BSVZRL-80 Analog Devices Inc, AD9272BSVZRL-80 Datasheet - Page 33

• Manufacturer Part Number: AD9272BSVZRL-80
• Description: 12Bit 80 MSPS Octal ADC
• Manufacturer: Analog Devices Inc
• Type: Ultrasound Receiversr

Specifications of AD9272BSVZRL-80

• Design Resources: Powering AD9272 with ADP5020 Switching Regulator PMU for Increased Efficiency (CN0135)
• Resolution (bits): 12 b
• Sampling Rate (per Second): 80M
• Data Interface: Serial
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 1.8V, 3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9272-65EBZ - BOARD EVAL AD9272
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

By asserting the PDWN pin high, the AD9272 is placed into
power-down mode. In this state, the device typically dissipates
2 mW. During power-down, the LVDS output drivers are placed
into a high impedance state. The AD9272 returns to normal
operating mode when the PDWN pin is pulled low. This pin is
both 1.8 V and 3.3 V tolerant.
By asserting the STBY pin high, the AD9272 is placed into a
standby mode. In this state, the device typically dissipates
150 mW. During standby, the entire part is powered down
except the internal references. The LVDS output drivers are
placed into a high impedance state. This mode is well suited for
applications that require power savings because it allows the
device to be powered down when not in use and then quickly
powered up. The time to power this device back up is also greatly
reduced. The AD9272 returns to normal operating mode when
the STBY pin is pulled low. This pin is both 1.8 V and 3.3 V
tolerant.
In power-down mode, low power dissipation is achieved by
shutting down the reference buffer, PLL, and biasing networks.
The decoupling capacitors on VREF are discharged when
entering power-down mode and must be recharged when
returning to normal operation. As a result, the wake-up time is
related to the time spent in the power-down mode: shorter cycles
result in proportionally shorter wake-up times. To restore the
device to full operation, approximately 0.5 ms is required when
using the recommended 1 μF and 0.1 μF decoupling capacitors
on the VREF pin and 0.01 μF on the GAIN± pins. Most of this
time is dependent on the gain decoupling: higher value decoupling
capacitors on the GAIN± pins result in longer wake-up times.
There are a number of other power-down options available when
using the SPI port interface. The user can individually power
down each channel or put the entire device into standby mode.
This allows the user to keep the internal PLL powered up when fast
wake-up times are required. The wake-up time is slightly dependent
on gain. To achieve a 1 μs wake-up time when the device is in
standby mode, 0.8 V must be applied to the GAIN± pins. See
Table 17 for more details on using these features.
Digital Outputs and Timing
The AD9272 differential outputs conform to the ANSI-644 LVDS
standard on default power-up. This can be changed to a low power,
reduced signal option similar to the IEEE 1596.3 standard by
using Register 14, Bit 6 or via the SPI. This LVDS standard can
further reduce the overall power dissipation of the device by
approximately 36 mW.
The LVDS driver current is derived on chip and sets the output
current at each output equal to a nominal 3.5 mA. A 100 Ω differ-
ential termination resistor placed at the LVDS receiver inputs
results in a nominal 350 mV swing at the receiver.
Rev. C | Page 33 of 44
The AD9272 LVDS outputs facilitate interfacing with LVDS
receivers in custom ASICs and FPGAs that have LVDS capability
for superior switching performance in noisy environments.
Single point-to-point net topologies are recommended with a
100 Ω termination resistor placed as close to the receiver as
possible. No far-end receiver termination and poor differential
trace routing may result in timing errors. It is recommended
that the trace length be no longer than 24 inches and that the
differential output traces be kept close together and at equal
lengths. An example of the FCO, DCO, and data stream with
proper trace length and position can be found in Figure 63.
An example of the LVDS output using the ANSI-644 standard
(default) data eye and a time interval error (TIE) jitter histogram
with trace lengths less than 24 inches on regular FR-4 material is
shown in Figure 64. Figure 65 shows an example of the trace
lengths exceeding 24 inches on regular FR-4 material. Notice
that the TIE jitter histogram reflects the decrease of the data eye
opening as the edge deviates from the ideal position; therefore,
the user must determine if the waveforms meet the timing budget
of the design when the trace lengths exceed 24 inches.
Additional SPI options allow the user to further increase the
internal termination (and therefore increase the current) of all
eight outputs in order to drive longer trace lengths (see Figure 66).
Even though this produces sharper rise and fall times on the
data edges, is less prone to bit errors, and improves frequency
distribution (see Figure 66), the power dissipation of the DRVDD
supply increases when this option is used.
In cases that require increased driver strength to the DCO± and
FCO± outputs because of load mismatch, Register 0x15 allows
the user to double the drive strength. To do this, set the appropriate
bit in Register 0x05. Note that this feature cannot be used with
Bit 4 and Bit 5 in Register 0x15 because these bits take precedence
over this feature. See Table 17 for more details.
Figure 63. LVDS Output Timing Example in ANSI-644 Mode (Default)
CH1 500mV/DIV = DCO
CH2 500mV/DIV = DATA
CH3 500mV/DIV = FCO
5.0ns/DIV
AD9272