AD9510/PCBZ Analog Devices Inc, AD9510/PCBZ Datasheet - Page 15

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AD9510/PCBZ

Manufacturer Part Number
AD9510/PCBZ
Description
800MHz PLL Clock Dist Eval Bd.
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9510/PCBZ

Main Purpose
Timing, Clock Distribution
Utilized Ic / Part
AD9510
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
SERIAL CONTROL PORT
Table 8.
Parameter
CSB, SCLK (INPUTS)
SDIO (WHEN INPUT)
SDIO, SDO (OUTPUTS)
TIMING
FUNCTION PIN
Table 9.
Parameter
INPUT CHARACTERISTICS
RESET TIMING
SYNC TIMING
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
Output Logic 1 Voltage
Output Logic 0 Voltage
Clock Rate (SCLK, 1/t
Pulse Width High, t
Pulse Width Low, t
SDIO to SCLK Setup, t
SCLK to SDIO Hold, t
SCLK to Valid SDIO and SDO, t
CSB to SCLK Setup and Hold, t
CSB Minimum Pulse Width High, t
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Capacitance
Pulse Width Low
Pulse Width Low
PWL
PWH
DH
SCLK
DS
)
Min
2.0
50
1.5
DV
S
, t
H
PWH
Typ
110
2
Max
0.8
1
Unit
V
V
μA
μA
pF
ns
High speed clock cycles
Min
2.0
2.0
2.7
16
16
2
1
6
2
3
Rev. A | Page 15 of 60
Typ
110
2
10
10
2
Max
0.8
1
0.8
0.4
25
Test Conditions/Comments
The FUNCTION pin has a 30 kΩ internal pull-down resistor.
This pin should normally be held high. Do not leave NC.
High speed clock is CLK1 or CLK2,
whichever is being used for distribution
Unit
V
V
μA
μA
pF
V
V
nA
nA
pF
V
V
MHz
ns
ns
ns
ns
ns
ns
ns
Test Conditions/Comments
CSB and SCLK have 30 kΩ
internal pull-down resistors
AD9510

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