AD9510/PCBZ Analog Devices Inc, AD9510/PCBZ Datasheet - Page 54

• Manufacturer Part Number: AD9510/PCBZ
• Description: 800MHz PLL Clock Dist Eval Bd.
• Manufacturer: Analog Devices Inc

Specifications of AD9510/PCBZ

• Main Purpose: Timing, Clock Distribution
• Utilized Ic / Part: AD9510
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9510
Reg.
Addr.
(Hex) Bit(s) Name
45
45
45
45
45
45
45
46
47
48
(4A)
(4C)
(4E)
(50)
(52)
(54)
(56)
48
(4A)
(4C)
(4E)
(50)
(52)
(54)
(56)
49
(4B)
(4D)
(4F)
(51)
(53)
(55)
(57)
49
(4B)
(4D)
(4F)
(51)
(53)
(55)
(57)
<0>
<1>
<2>
<3>
<4>
<5>
<7:6>
<7:0>
<7:0>
<3:0> Divider High
<7:4> Divider Low
<3:0> Phase Offset
<4>
Clock Select
CLK1 Power-Down 1 = CLK1 Input Is Powered Down (Default = 0b)
CLK2 Power-Down 1 = CLK2 Input Is Powered Down (Default = 0b)
Prescaler Clock
Power-Down
REFIN Power-Down 1 = Power-Down REFIN (Default = 0b)
All Clock Inputs
Power-Down
OUT0
(OUT1)
(OUT2)
(OUT3)
(OUT4)
(OUT5)
(OUT6)
(OUT7)
OUT0
(OUT1)
(OUT2)
(OUT3)
(OUT4)
(OUT5)
(OUT6)
(OUT7)
OUT0
(OUT1)
(OUT2)
(OUT3)
(OUT4)
(OUT5)
(OUT6)
(OUT7)
Start
OUT0
(OUT1)
(OUT2)
(OUT3)
(OUT4)
(OUT5)
(OUT6)
(OUT7)
Description
0: CLK2 Drives Distribution Section
1: CLK1 Drives Distribution Section (Default)
1 = Shut Down Clock Signal to PLL Prescaler (Default = 0b)
1 = Power-Down CLK1 and CLK2 Inputs and Associated Bias and Internal Clock Tree;
(Default = 0b)
Not Used
Not Used
Not Used
Number of Clock Cycles Divider Output Stays High
Number of Clock Cycles Divider Output Stays Low
Phase Offset (Default = 0000b)
Selects Start High or Start Low
(Default = 0b)
Rev. A | Page 54 of 60