AD9518-2ABCPZ Analog Devices Inc, AD9518-2ABCPZ Datasheet - Page 24
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AD9518-2ABCPZ
Manufacturer Part Number
AD9518-2ABCPZ
Description
6-Output Clock Generator With 2.8GHz
Manufacturer
Analog Devices Inc
Type
Clock Generator, Fanout Distributionr
Datasheet
1.AD9518-2ABCPZ-RL7.pdf
(64 pages)
Specifications of AD9518-2ABCPZ
Pll
Yes
Input
CMOS, LVDS, LVPECL
Output
LVPECL
Number Of Circuits
1
Ratio - Input:output
1:6
Differential - Input:output
Yes/Yes
Frequency - Max
2.33GHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-LFCSP
Frequency-max
2.33GHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
AD9518-2
Internal VCO and Clock Distribution
When using the internal VCO and PLL, the VCO divider must
be employed to ensure that the frequency presented to the channel
dividers does not exceed its specified maximum frequency
(1.6 GHz, see Table 3). The internal PLL uses an external loop
filter to set the loop bandwidth. The external loop filter is also
crucial to the loop stability.
When using the internal VCO, it is necessary to calibrate the
VCO (Register 0x018[0]) to ensure optimal performance.
For internal VCO and clock distribution applications, the
register settings shown in Table 23 should be used.
REFIN (REF1)
REFIN (REF2)
BYPASS
RESET
SYNC
SCLK
SDIO
SDO
CLK
CLK
PD
CS
LF
REF1
REF2
REGULATOR (LDO)
LOW DROPOUT
VCO
AD9518-2
CONTROL
DIGITAL
SWITCHOVER
SERIAL
STATUS
LOGIC
REFERENCE
PORT
REF_ SEL
STATUS
VS
PRESCALER
2, 3, 4, 5, OR 6
1
P, P + 1
DIVIDE BY
GND
0
VCO STATUS
N DIVIDER
DIVIDER
Figure 28. Internal VCO and Clock Distribution
R
COUNTERS
DISTRIBUTION
REFERENCE
A/B
RSET
Rev. A | Page 24 of 64
DIVIDE BY
DIVIDE BY
DIVIDE BY
1 TO 32
1 TO 32
1 TO 32
PROGRAMMABLE
PROGRAMMABLE
R DELAY
N DELAY
REFMON
Table 23. Settings When Using an Internal VCO
Register
0x010[1:0] = 00b
0x010 to 0x01E
0x018[0] = 0b,
0x232[0] = 1b
0x1E0[2:0]
0x1E1[0] = 0b
0x1E1[1] = 1b
0x018[0] = 1b,
0x232[0] = 1b
FREQUENCY
DETECTOR
DETECT
PHASE
LOCK
Function
PLL normal operation (PLL on).
PLL settings. Select and enable a reference
input; set R, N (P, A, B), PFD polarity, and I
according to the intended loop configuration.
Reset VCO calibration. This process is not
required the first time after power-up, but it
must be performed subsequently.
Set VCO divider to divide-by-2, divide-by-3,
divide-by-4, divide-by-5, or divide-by-6.
Use the VCO divider as source for the
distribution section.
Select VCO as the source.
Initiate VCO calibration.
CPRSET VCP
CHARGE
PUMP
HOLD
LVPECL
LVPECL
LVPECL
OUT0
OUT0
OUT1
OUT1
OUT2
OUT2
OUT3
OUT3
OUT4
OUT4
OUT5
OUT5
LD
CP
STATUS
CP