AD9522-5/PCBZ Analog Devices Inc, AD9522-5/PCBZ Datasheet - Page 41

• Manufacturer Part Number: AD9522-5/PCBZ
• Description: 12/24 Channel Clock Gen 2,0GH
• Manufacturer: Analog Devices Inc

Specifications of AD9522-5/PCBZ

• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9522-5
• Primary Attributes: 12 LVDS/24 CMOS Outputs
• Secondary Attributes: I²C & SPI Interfaces
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DIVIDER 0
DIVIDER 1
DIVIDER 2
By giving each divider a different phase offset, output-to-output
delays can be set in increments of the channel divider input
clock cycle. Figure 38 shows the results of setting such a coarse
offset between outputs.
Synchronizing the Outputs—SYNC Function
The AD9522 clock outputs can be synchronized to each other.
Outputs can be individually excluded from synchronization.
Synchronization consists of setting the nonexcluded outputs to
a preset set of static conditions. These conditions include the
divider ratio and phase offsets for a given channel divider. This
allows the user to specify different divide ratios and phase offsets
for each of the four channel dividers. Releasing the SYNC pin
allows the outputs to continue clocking with the preset conditions
applied.
Synchronization of the outputs is executed in the following ways:
•
•
•
•
•
The most common way to execute the SYNC function is to use
the SYNC pin to perform a manual synchronization of the outputs.
This requires a low going signal on the SYNC pin, which is held
DIVIDER INPUT
CHANNEL
The SYNC pin is forced low and then released (manual sync).
By setting and then resetting any one of the following three
bits: the soft SYNC bit (0x230[0]), the soft reset bit
(0x000[5] [mirrored]), and the power-down distribution
reference bit (0x230[1]).
Synchronization of the outputs can be executed as part of
the chip power-up sequence.
The RESET pin is forced low and then released (chip reset).
The PD pin is forced low and then released (chip power-
down).
SH = 0
PO = 0
SH = 0
PO = 1
SH = 0
PO = 2
Figure 38. Effect of Coarse Phase Offset (or Delay)
0
1
Tx
2
3
1 × Tx
2 × Tx
4
CHANNEL DIVIDER OUTPUTS
5
DIV = 4, DUTY = 50%
6
7
8
9 10 11 12 13 14 15
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low and then released when synchronization is desired. The
timing of the SYNC operation is shown in
VCO divider) and in
There is an uncertainty of up to one cycle of the clock at the
input to the channel divider due to the asynchronous nature of
the SYNC signal with respect to the clock edges inside the AD9522.
The pipeline delay from the SYNC rising edge to the beginning
of the synchronized output clocking is between 14 cycles and
15 cycles of clock at the channel divider input, plus one cycle of
the VCO divider input (see
channel divider input (see
VCO divider is used. Cycles are counted from the rising edge of
the signal. In addition, there is an additional 1.2 ns (typical) delay
from the SYNC signal to the internal synchronization logic, as well
as the propagation delay of the output driver. The driver
propagation delay is approximately 100 ps for the LVDS driver
and approximately 1.5 ns for the CMOS driver.
Another common way to execute the SYNC function is by
setting and resetting the soft SYNC bit at 0x230[0]. Both setting
and resetting of the soft SYNC bit require an update all registers
(0x232[0] = 1b) operation to take effect.
A SYNC operation brings all outputs that have not been excluded
(by the ignore SYNC bit) to a preset condition before allowing
the outputs to begin clocking in synchronicity. The preset condition
takes into account the settings of each channel start high bit and
its phase offset. These settings govern both the static state of each
output when the SYNC operation is happening and the state
and relative phase of the outputs when they begin clocking
again upon completion of the SYNC operation. A SYNC operation
must take place in order for the phase offset settings to take effect.
The AD9522 differential LVDS outputs are four groups of three,
sharing a channel divider per triplet. In the case of CMOS, each
LVDS differential pair can be configured as two single-ended
CMOS outputs. The synchronization conditions apply to all of
the drivers that belong to that channel divider.
Each channel (a divider and its outputs) can be excluded from
any SYNC operation by setting the ignore SYNC bit of the channel.
Channels that are set to ignore SYNC (excluded channels) do
not set their outputs static during a SYNC operation, and their
outputs are not synchronized with those of the included channels.
Figure 40
Figure 40
Figure 39
(the VCO divider is not used).
), depending on whether the
) or one cycle of the
Figure 39
AD9522-5
(using the