AD9522-5/PCBZ Analog Devices Inc, AD9522-5/PCBZ Datasheet - Page 64

• Manufacturer Part Number: AD9522-5/PCBZ
• Description: 12/24 Channel Clock Gen 2,0GH
• Manufacturer: Analog Devices Inc

Specifications of AD9522-5/PCBZ

• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9522-5
• Primary Attributes: 12 LVDS/24 CMOS Outputs
• Secondary Attributes: I²C & SPI Interfaces
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Reg.
Addr
(Hex) Bit(s) Name
01A
01A
01A
AD9522-5
[7]
[6]
[5:0] LD pin
Enable STATUS
pin divider
Ref freq monitor
threshold
control
Description
Enables a divide-by-4 on the STATUS pin. This makes it easier to look at low duty-cycle signals out of the
R and N dividers.
[7] = 0; divide-by-4 disabled on STATUS pin (default).
[7] = 1; divide-by-4 enabled on STATUS pin.
Sets the reference (REF1/REF2) frequency monitor’s detection threshold frequency. This does not affect the CLK
frequency monitor’s detection threshold (see Table 14, REF1, REF2, and CLK frequency status monitor parameter).
[6] = 0; frequency valid if frequency is above 1.02 MHz (default).
[6] = 1; frequency valid if frequency is above 8 kHz.
Selects the signal that is connected to the LD pin.
[5] [4] [3]
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
[2]
0
0
0
0
1
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
[1]
0
0
1
1
0
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
Rev. 0 | Page 64 of 76
[0]
0
1
0
1
0
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Level or
Dynamic
Signal
LVL
DYN
DYN
HIZ
CUR
LVL
LVL
DYN
DYN
DYN
DYN
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
DYN
DYN
DYN
DYN
LVL
LVL
LVL
LVL
LVL
Ground (dc); for all other cases of 0XXXXX not specified.
Signal at LD Pin
Digital lock detect (high = lock; low = unlock, default).
P-channel, open-drain lock detect (analog lock detect).
N-channel, open-drain lock detect (analog lock detect).
Tristate (high-Z) LD pin.
Current source lock detect (110 μA when DLD is true).
The selections that follow are the same as for REFMON.
Ground (dc).
REF1 clock (differential reference when in differential mode).
REF2 clock (not applicable in differential mode).
Selected reference to PLL (differential reference when in
differential mode).
Unselected reference to PLL (not available in differential mode).
Status of selected reference (status of differential reference);
active high.
Status of unselected reference (not available in differential
mode); active high.
Status of REF1 frequency (active high).
Status of REF2 frequency (active high).
(Status of REF1 frequency) AND (status of REF2 frequency).
(DLD) AND (status of selected reference) AND (status of CLK).
Status of CLK frequency (active high).
Selected reference (low = REF1, high = REF2).
DLD; active high.
Holdover active (active high).
Not applicable, do not use.
VS (PLL supply).
REF1 clock (differential reference when in differential mode).
REF2 clock (not available in differential mode).
Selected reference to PLL (differential reference when in
differential mode).
Unselected reference to PLL (not available when in differential
mode).
Status of selected reference (status of differential reference);
active low.
Status of unselected reference (not available in differential
mode); active low.
Status of REF1 frequency (active low).
Status of REF2 frequency (active low).
(Status of REF1 frequency) AND (status of REF2 frequency).