AD9552BCPZ-REEL7 Analog Devices Inc, AD9552BCPZ-REEL7 Datasheet - Page 17

• Manufacturer Part Number: AD9552BCPZ-REEL7
• Description: Precision Clock Translator
• Manufacturer: Analog Devices Inc
• Type: Clock Generatorr

Specifications of AD9552BCPZ-REEL7

• Design Resources: Clock Distribution Circuit with Pin-Programmable Output Frequency, Output Logic Levels, and Fanout (CN0152)
• Pll: Yes
• Input: Clock, Crystal
• Output: CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: No/Yes
• Frequency - Max: 900MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LFCSP
• Frequency-max: 900MHz
• Number Of Elements: 1
• Pll Input Freq (min): 6.6MHz
• Pll Input Freq (max): 112.5MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: LFCSP EP
• Output Frequency Range: 0 to 900MHz
• Operating Temperature Classification: Industrial
• Pin Count: 32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PART INITIALIZATION AND AUTOMATIC POWER-
ON RESET
The AD9552 has an internal power-on reset circuit. At power-up,
internal logic relies on the internal reference monitor to select
either the crystal oscillator or the reference input and then
initiates VCO calibration using whichever is found. If both are
present, the external reference path is chosen.
VCO calibration is required in order for the device to lock. If
the input reference signal is not present, VCO calibration waits
until a valid input reference is present. As soon as an input
reference signal is present, VCO calibration starts.
If the user wishes to use the crystal oscillator input even if the
reference input is present, the user needs to set Bit 0 (use crystal
resonator) in Register 0x1D.
Any change to the preset frequency selection pins or the PLL
divide ratios requires the user to recalibrate the VCO.
OUTPUT/INPUT FREQUENCY RELATIONSHIP
The frequency at OUT1 and OUT2 is a function of the PLL
feedback divider values (N, FRAC, and MOD) and the output
divider values (P
frequency at OUT1 and OUT2 (f
are as follows.
where:
f
K is the input mode scale factor.
N is the integer feedback divider value.
FRAC and MOD are the fractional feedback divider values.
P
The numerator of the f
factor, which has an integer part (N) due to an integer divider
along with an optional fractional part (FRAC/MOD) associated
with the feedback SDM.
The following constraints apply:
Note that N
of N
SDM is disabled or N
depends on the 2× frequency multiplier. K = 1 when the 2×
frequency multiplier is bypassed, or K = 2 when it is enabled.
REF
0
and P
is the input reference or crystal resonator frequency.
MIN
f
N
N
FRAC
K
P
P
MOD
OUT2
f
1
OUT
0
MIN
∈
∈
∈
∈
depends on the state of the SDM. N
1
{
{ }
{
1
= f
are the OUT1 divider values.
{
1
1
N
4
∈
=
∈
2 ,
, 2 ,
∈
MIN
, 5 ,
OUT1
MIN
{
{
{
f
36
, 1 L
L
0 L
REF
L
and K can each be one of two values. The value
, 1 ,
, 2
,
,
0
,
N
,
47
63
⎛
⎜
⎜
⎝
11
and P
MIN
K
}
}
}
, 1 ,
, 1 ,
×
MIN
OUT1
+
048
N
048
1
, 1
). The equations that define the
= 47 when it is enabled. The value of K
P
+
equation contains the feedback division
0
L
,
,
575
P
575
FRAC
MOD
1
,
255
}
}
⎞
⎟
⎟
⎠
OUT1
}
and f
OUT2
MIN
, respectively)
= 36 when the
Rev. C | Page 17 of 32
The frequency at the input to the PFD (f
follows:
The operating range of the VCO (3.35 GHz ≤ f
places the following constraint on f
CALCULATING DIVIDER VALUES
This section provides a three-step procedure for calculating the
divider values when given a specific f
frequency of either the REF input signal source or the external
crystal resonator). The computation process is described in
general terms, but a specific example is provided for clarity.
The example is based on a frequency control pin setting of
A[2:0] = 111 (see Table 9) and Y[5:0] = 101000 (see Table 10),
yielding the following:
1.
2.
f
f
f
Determine the output divide factor (ODF).
Note that the VCO frequency (f
4050 MHz. The ratio, f
Given the specified value of f
range of f
must be an integer, which means that ODF = 6 (because 6
is the only integer between 5.2 and 6.3).
Determine suitable values for P
The ODF is the product of the two output dividers, so
ODF = P
for the given example. Therefore, P
that P
the Output/Input Frequency Relationship section). These
constraints lead to the single solution: P
Although this particular example yields a single solution
for the output divider values with f
f
one. For example, if f
34 to 40. This leads to an assortment of possible values for
P0 and P1, as shown in Table 12.
Table 12. Combinations for P
PFD
⎛
⎜
⎜
⎝
REF
OUT1
OUT1
P
4
4
5
5
6
7
8
9
10
N
0
= 26 MHz
= K × f
3350
+
= 625 × (66/64) MHz
frequencies result in multiple ODFs rather than just
0
FRAC
MOD
and P
0
VCO
P
REF
1
⎞
⎟
⎟
⎠
. It has already been determined that ODF = 6
, the ODF spans a range of 5.2 to 6.3. The ODF
MHz
1
are both integers and that 4 ≤ P
≤
f
OUT1
P
9
10
7
8
6
5
5
4
4
PFD
VCO
1
/f
= 100 MHz the ODF ranges from
≤
OUT1
⎛
⎜
⎜
⎝
N
OUT1
PFD
, indicates the required ODF.
4050
OUT1
+
0
0
VCO
and P
and P
:
FRAC
MOD
(~644.53 MHz) and the
0
P
OUT1
/f
) spans 3350 MHz to
1
PFD
REF
= 6 with the constraints
⎞
⎟
⎟
⎠
≈ 644.53 MHz, some
) is calculated as
1
1
ratio (f
MHz
.
0
= 6 and P
ODF (P
36
40
35
40
36
35
40
36
40
VCO
REF
≤ 4.05 GHz)
0
≤ 11 (see
AD9552
is the
0
× P
1
= 1.
1
)