AD9552BCPZ-REEL7 Analog Devices Inc, AD9552BCPZ-REEL7 Datasheet - Page 22

• Manufacturer Part Number: AD9552BCPZ-REEL7
• Description: Precision Clock Translator
• Manufacturer: Analog Devices Inc
• Type: Clock Generatorr

Specifications of AD9552BCPZ-REEL7

• Design Resources: Clock Distribution Circuit with Pin-Programmable Output Frequency, Output Logic Levels, and Fanout (CN0152)
• Pll: Yes
• Input: Clock, Crystal
• Output: CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: No/Yes
• Frequency - Max: 900MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LFCSP
• Frequency-max: 900MHz
• Number Of Elements: 1
• Pll Input Freq (min): 6.6MHz
• Pll Input Freq (max): 112.5MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: LFCSP EP
• Output Frequency Range: 0 to 900MHz
• Operating Temperature Classification: Industrial
• Pin Count: 32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9552
SCLK
SCLK
SCLK
SDIO
SDIO
SDIO
CS
CS
CS
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SCLK
SDIO
CS
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R/W
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W1
R/W
A0 A1 A2 A3 A4
SCLK
SDIO
W0
CS
W1
A12
16-BIT INSTRUCTION HEADER
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
W0
A12
t
S
R/W
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
t
16-BIT INSTRUCTION HEADER
16-BIT INSTRUCTION HEADER
Figure 26. Serial Control Port Write—MSB First, 16-Bit Instruction, Timing Measurements
DS
A5 A6 A7 A8 A9 A10 A11 A12
W1
t
t
Figure 24. Serial Control Port Write—MSB First, 16-Bit Instruction, Two Bytes Data
Figure 25. Serial Control Port Read—MSB First, 16-Bit Instruction, Four Bytes Data
DS
Figure 28. Serial Control Port Write—LSB First, 16-Bit Instruction, Two Bytes Data
S
SCLK
SDIO
W0
t
DH
CS
BIT N
Figure 27. Timing Diagram for Serial Control Port Register Read
A12
t
t
LOW
HIGH
t
DH
t
HIGH
A11
Figure 29. Serial Control Port Timing—Write
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
DATA BIT N
t
REGISTER (N) DATA
CLK
A10
t
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t
DV
W0
LOW
A9
t
CLK
W1
A8
R/W
BIT N + 1
DATA BIT N – 1
D0
D7 D6 D5 D4 D3
A7
REGISTER (N – 1) D ATA
D1
REGISTER (N) DATA
REGISTER (N) DATA
A6
D2 D3 D4
A5
D4
D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
D3
REGISTER (N – 2) D ATA
D2
REGISTER (N – 1) D ATA
REGISTER (N + 1) D ATA
D1
t
H
D0
t
H
REGISTER (N – 3) D ATA
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