AD9601BCPZ-200 Analog Devices Inc, AD9601BCPZ-200 Datasheet - Page 22

• Manufacturer Part Number: AD9601BCPZ-200
• Description: IC,A/D CONVERTER,SINGLE,10-BIT,CMOS,LLCC,56PIN
• Manufacturer: Analog Devices Inc

Specifications of AD9601BCPZ-200

• Number Of Bits: 10
• Sampling Rate (per Second): 200M
• Data Interface: Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 291mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9601-250EBZ - BOARD EVALUATION AD9601-250
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9601
Table 10. Serial Timing Definitions
Parameter
t
t
t
t
t
t
t
t
t
Table 11. Output Data Format
Input (V)
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
DS
DH
CLK
S
H
HI
LO
EN_SDIO
DIS_SDIO
Condition (V)
< 0.62
= 0.62
= 0
= 0.62
> 0.62 + 0.5 LSB
Timing (minimum, ns)
5
2
40
5
2
16
16
1
5
Offset Binary Output Mode
D11 to D0
0000 0000 0000
0000 0000 0000
0000 0000 0000
1111 1111 1111
1111 1111 1111
Description
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the clock
Setup time between CSB and SCLK
Hold time between CSB and SCLK
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK
falling edge (not shown in Figure 44)
Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK
rising edge (not shown in Figure 44)
Rev. 0 | Page 22 of 32
Twos Complement Mode
D11 to D0
0000 0000 0000
0000 0000 0000
0000 0000 0000
1111 1111 1111
1111 1111 1111
Gray Code Mode
(SPI Accessible)
D11 to D0
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
OR
1
0
0
0
1