AD9640ABCPZ-125 Analog Devices Inc, AD9640ABCPZ-125 Datasheet - Page 41

• Manufacturer Part Number: AD9640ABCPZ-125
• Description: 14Bit 125Msps Dual 1.8V PB Free ADC
• Manufacturer: Analog Devices Inc

Specifications of AD9640ABCPZ-125

• Design Resources: Interfacing ADL5534 to AD9640 High Speed ADC (CN0049)
• Number Of Bits: 14
• Sampling Rate (per Second): 125M
• Data Interface: Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 846mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CONFIGURATION WITHOUT THE SPI
In applications that do not interface to the SPI control registers,
the SDIO/DCS pin, the SCLK/DFS pin, the SMI SDO/OEB pin,
and the SMI SCLK/PDWN pin serve as standalone, CMOS-
compatible control pins. When the device is powered up, it is
assumed that the user intends to use the pins as static control
lines for the duty cycle stabilizer, output data format, output
enable, and power-down feature control. In this mode, the CSB
chip select should be connected to AVDD, which disables the
serial port interface.
Table 23. Mode Selection
Pin
SDIO/DCS
SCLK/DFS
SMI SDO/OEB
SMI SCLK/PDWN
SCLK
SDIO
CSB
DON’T CARE
DON’T CARE
t
S
External
Voltage
AVDD (default)
AGND
AVDD
AGND (default)
AVDD
AGND (default)
AVDD
AGND (default)
R/W
t
DS
W1
W0
t
DH
Configuration
Duty cycle stabilizer enabled.
Duty cycle stabilizer disabled.
Twos complement enabled.
Offset binary enabled.
Outputs in high impedance.
Outputs enabled.
Chip in power-down or
standby.
Normal operation.
A12
t
HIGH
A11
Figure 73. Serial Port Interface Timing Diagram
t
LOW
A10
A9
Rev. B | Page 41 of 52
t
CLK
A8
A7
SPI ACCESSIBLE FEATURES
A brief description of general features accessible via the SPI
follows. These features are described in detail in the AN-877
Application Note, Interfacing to High Speed ADCs via SPI. The
AD9640 part-specific features are described in detail following
Table 25, the external memory map register table.
Table 24. Features Accessible Using the SPI
Feature Name
Modes
Clock
Offset
Test I/O
Output Mode
Output Phase
Output Delay
VREF
D5
D4
Description
Allows user to set either power-down mode or
standby mode.
Allows user to access the DCS via the SPI.
Allows user to digitally adjust the converter
offset.
Allows user to set test modes to have known
data on output bits.
Allows user to set up outputs.
Allows user to set the output clock polarity.
Allows user to vary the DCO delay.
Allows user to set the reference voltage.
D3
D2
D1
D0
t
H
DON’T CARE
AD9640
DON’T CARE