AD9640ABCPZ-150 Analog Devices Inc, AD9640ABCPZ-150 Datasheet - Page 12

• Manufacturer Part Number: AD9640ABCPZ-150
• Description: 14Bit 150Msps Dual 1.8V PB Free ADC
• Manufacturer: Analog Devices Inc

Specifications of AD9640ABCPZ-150

• Design Resources: Interfacing ADL5534 to AD9640 High Speed ADC (CN0049)
• Number Of Bits: 14
• Sampling Rate (per Second): 150M
• Data Interface: Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 938mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Number Of Elements: 2
• Resolution: 14Bit
• Architecture: Pipelined
• Sample Rate: 150MSPS
• Input Polarity: Bipolar
• Input Type: Voltage
• Rated Input Volt: ±1V
• Differential Input: Yes
• Power Supply Requirement: Analog and Digital
• Single Supply Voltage (typ): 1.8V
• Single Supply Voltage (min): 1.7V
• Single Supply Voltage (max): 1.9V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Differential Linearity Error: -0.95LSB/1.5LSB
• Integral Nonlinearity Error: ±5LSB
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: LFCSP EP
• Input Signal Type: Differential
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9640
TIMING SPECIFICATIONS
Table 8.
Parameter
SYNC TIMING REQUIREMENTS
SPI TIMING REQUIREMENTS
SPORT TIMING REQUIREMENTS
Timing Diagrams
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SSYNC
HSYNC
DS
DH
CLK
S
H
HIGH
LOW
EN_SDIO
DIS_SDIO
CSSCLK
SSCLKSDO
SSCLKSDFS
CH A/B DATA
CH A/B FAST
DCOA/DCOB
DETECT
CLK+
CLK–
Figure 2. CMOS Output Mode Data and Fast Detect Output Timing (Fast Detect Mode 0)
Conditions
SYNC to rising edge of CLK setup time
SYNC to rising edge of CLK hold time
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
SCLK pulse width high
SCLK pulse width low
Time required for the SDIO pin to switch from an input to an
output relative to the SCLK falling edge
Time required for the SDIO pin to switch from an output to
an input relative to the SCLK rising edge
Delay from rising edge of CLK+ to rising edge of SMI SCLK
Delay from rising edge of SMI SCLK to SMI SDO
Delay from rising edge of SMI SCLK to SMI SDFS
N – 13
N – 3
N
t
S
t
t
A
PD
N – 12
N – 2
N + 1
t
CLK
t
H
N – 11
N + 2
N – 1
Rev. B | Page 12 of 52
N – 10
N + 3
N
t
DCO
N – 9
N + 1
N + 4
N – 8
N + 2
N + 5
t
CLK
N + 6
N + 3
N – 7
N + 7
N – 6
N + 4
Min
2
2
40
2
2
10
10
10
10
3.2
−0.4
−0.4
N + 8
N – 5
N + 5
Typ
0.24
0.40
4.5
0
0
N – 4
N + 6
Max
6.2
+0.4
+0.4
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns