AD9640ABCPZ-150 Analog Devices Inc, AD9640ABCPZ-150 Datasheet - Page 39

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AD9640ABCPZ-150

Manufacturer Part Number
AD9640ABCPZ-150
Description
14Bit 150Msps Dual 1.8V PB Free ADC
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9640ABCPZ-150

Design Resources
Interfacing ADL5534 to AD9640 High Speed ADC (CN0049)
Number Of Bits
14
Sampling Rate (per Second)
150M
Data Interface
Serial, SPI™
Number Of Converters
2
Power Dissipation (max)
938mW
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LFCSP
Number Of Elements
2
Resolution
14Bit
Architecture
Pipelined
Sample Rate
150MSPS
Input Polarity
Bipolar
Input Type
Voltage
Rated Input Volt
±1V
Differential Input
Yes
Power Supply Requirement
Analog and Digital
Single Supply Voltage (typ)
1.8V
Single Supply Voltage (min)
1.7V
Single Supply Voltage (max)
1.9V
Dual Supply Voltage (typ)
Not RequiredV
Dual Supply Voltage (min)
Not RequiredV
Dual Supply Voltage (max)
Not RequiredV
Differential Linearity Error
-0.95LSB/1.5LSB
Integral Nonlinearity Error
±5LSB
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Package Type
LFCSP EP
Input Signal Type
Differential
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
CHANNEL/CHIP SYNCHRONIZATION
The AD9640 has a SYNC input that allows the user flexible
synchronization options for synchronizing the internal blocks.
The clock divider sync feature is useful to guarantee synchronized
sample clocks across multiple ADCs. The signal monitor block
can also be synchronized using the SYNC input allowing properties
of the input signal to be measured during a specific time period.
The input clock divider can be enabled to synchronize on a single
occurrence of the sync signal or on every occurrence. The signal
monitor block is synchronized on every SYNC input signal.
Rev. B | Page 39 of 52
The SYNC input is internally synchronized to the sample clock;
however, to ensure there is no timing uncertainty between multiple
parts, the SYNC input signal should be externally synchronized to
the input clock signal, meeting the setup and hold times shown
in Table 8. The SYNC input should be driven using a single-
ended CMOS-type signal.
AD9640

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