AD9739-CMTS-EBZ Analog Devices Inc, AD9739-CMTS-EBZ Datasheet - Page 28

• Manufacturer Part Number: AD9739-CMTS-EBZ
• Description: 14 Bit 2.5 GSPS DAC
• Manufacturer: Analog Devices Inc

Specifications of AD9739-CMTS-EBZ

• Number Of Dac's: 1
• Number Of Bits: 14
• Outputs And Type: 1, Differential
• Sampling Rate (per Second): 2.5G
• Data Interface: SPI™
• Dac Type: Current
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9739
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9739
Name
LVDS_
REC_STAT7
LVDS_
REC_STAT8
LVDS_
REC_STAT9
CROSS_
CNT1
CROSS_
CNT2
PHS_DET
MU_DUTY
MU_CNT1
MU_CNT2
MU_CNT3
MU_CNT4
MU_STAT1
RSVD
RSVD
ANA_CNT1
ANA_CNT2
RSVD
PART ID
SPI REGISTERS
Reading these registers returns previously written values for all defined register bits, unless otherwise noted.
Table 8. Mode Register (Register 0x00)
Register
Name
Mode
1
Table 9. Mode Register Bit Descriptions
Bit
Name
SDIO_DIR
LSB/MSB
Reset
Table 10. Power-Down Register (Register 0x01)
Register
Name
Power-Down
1
The two-digit number is the decimal representation of the address.
The two-digit number is the decimal representation of the address.
Read/Write
Read/write
Read/write
Read/write
Address
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x32
0x33
0x34
0x35
Address
0x00
Address
0x01
Bit 7
SYNCSH_
DEL[0]
SYNCSH_
DEL[8]
SYNC_TRK
_ON
N/A
N/A
N/A
MU_DUTY
AUTO_EN
N/A
MUDEL[0]
MUDEL[8]
Search_Tol
N/A
N/A
N/A
HDRM[7]
N/A
N/A
ID[7]
1
1
01
Description
0: input only, per SPI standard.
1: bidirectional, per SPI standard.
0: MSB first, per SPI standard.
1: LSB first, per SPI standard.
Change the LSB/MSB order in single-byte instructions only to avoid erratic behavior due to
bit order errors.
0: default. Bit is in the inactive state.
1: all programmable bits return to their default state except Register 0x00, which is
unaffected by the software reset. The software reset remains in effect until this bit is set to 0
(inactive state).
00
Bit 7
N/A
Bit 7
SDIO_DIR
Bit 6
N/A
SYNCSH_
DEL[7]
SYNC_INIT
_ON
N/A
N/A
N/A
POS/NEG
Slope
SrchMode
[1]
MUDEL[7]
Retry
N/A
N/A
N/A
HDRM[6]
N/A
N/A
ID[6]
Bit 6
N/A
Bit 5
LVDS_DCO_PD
Bit 5
N/A
SYNCSH_
DEL[6]
SYNC_LST
_LCK
N/A
N/A
PHS_DET
AUTO_EN
ADJ[5]
Mode[1]
SrchMode
[0]
MUDEL[6]
ContRst
N/A
N/A
N/A
HDRM[5]
N/A
N/A
ID[5]
Bit 6
LSB/MSB
Rev. 0 | Page 28 of 56
Bit 4
N/A
SYNCSH_
DEL[5]
SYNC_LCK
DIR_P
DIR_N
CMP_BST
ADJ[4]
Mode[0]
SetPhs[4]
MUDEL[5]
Guard[4]
N/A
N/A
N/A
HDRM[4]
N/A
N/A
ID[4]
Bit 4
LVDS_RCVR_PD
Bit 5
Reset
Bit 3
N/A
SYNCSH_
DEL[4]
RCVR_TRK
_ON
CLKP_
OFFSET[3]
CLKN_
OFFSET[3]
Bias[3]
ADJ[3]
Read
SetPhs[3]
MUDEL[4]
Guard[3]
N/A
N/A
N/A
HDRM[3]
N/A
N/A
ID[3]
Bit 4
N/A
Bit 3
N/A
Bit 2
N/A
SYNCSH_
DEL[3]
RCVR_FE_
ON
CLKP_
OFFSET[2]
CLKN_
OFFSET[2]
Bias[2]
ADJ[2]
Gain[1]
SetPhs[2]
MUDEL[3]
Guard[2]
N/A
N/A
N/A
HDRM[2]
N/A
ID[2]
N/A
Bit 3
N/A
Bit 2
N/A
Bit 1
N/A
SYNCSH_
DEL[2]
RCVR_LST_
LCK
CLKP_
OFFSET[1]
CLKN_
OFFSET[1]
Bias[1]
ADJ[1]
Gain[0]
SetPhs[1]
MUDEL[2]
Guard[1]
MU_LOST
N/A
N/A
HDRM[1]
MSEL[1]
N/A
ID[1]
Bit 1
CLK_REC_PD
Bit 2
N/A
Bit 0
N/A
SYNCSH_
DEL[1]
RCVR_LCK
CLKP_
OFFSET[0]
CLKN_
OFFSET[0]
Bias[0]
ADJ[0]
Enable
SetPhs[0]
MUDEL[1]
Guard[0]
MU_LKD
N/A
N/A
HDRM[0]
MSEL[0]
N/A
ID[0]
Bit 1
N/A
Reset Value for
Write Register
0
0
0
Bit 0
DAC_BIAS_PD
Default
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x42
0x40
0x00
0x0B
0x00
N/A
N/A
0xCA
0x03
N/A
0x40
Bit 0
N/A