AD9739-R2-EBZ Analog Devices Inc, AD9739-R2-EBZ Datasheet
AD9739-R2-EBZ
Specifications of AD9739-R2-EBZ
Related parts for AD9739-R2-EBZ
AD9739-R2-EBZ Summary of contents
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... Point-to-point wireless Instrumentation, automatic test equipment Radar, avionics GENERAL DESCRIPTION The AD9739 is a high performance, high frequency 14-bit DAC that provides sample rates up to 2500 MSPS, permitting multicarrier generation up to the Nyquist frequency in baseband mode and second and third Nyquist zones in mix mode ...
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... SPI Registers ................................................................................ 28 Applications Information .............................................................. 37 Analog Modes of Operation ..................................................... 37 LVDS Data Port Interface .......................................................... 37 Clocking the AD9739 ................................................................ 39 Applying Data to the AD9739 .................................................. 40 Mu Delay Controller .................................................................. 41 Mu Control Operation............................................................... 41 Search Mode ........................................................................... 41 Track Mode ............................................................................. 42 Mu Delay and Phase Readback ............................................ 42 ...
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... Use an external amplifier to drive any external load. 2 All power-down bits set (Register 0x01, Bit 0, Bit 1, Bit 4, Bit 5; Register 0x02, Bit 3 mA. FS Min 8.66 −1.0 3.1 1.70 3.10 1.70 Rev Page AD9739 Typ Max Unit 14 Bits ±1.3 LSB ±0.8 LSB 5.5 % 20.2 31 ...
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... AD9739 DIGITAL SPECIFICATIONS VDDA = VDD33 = 3.3 V, VDDC = VDD = 1 link, unless otherwise noted. Table 2. Parameter LVDS DATA INPUTS (DB0[13:0]P, DB0[13:0]N, DB1[13:0]P, DB1[13:0]N) DB Input Voltage Range Input Differential Threshold, V IDTH Input Differential Hysteresis, V – V IDTHH Receiver Differential Input Impedance, R LVDS Input Rate LVDS Minimum Data Valid Period (t ...
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... MHz OUT f = 2400 MSPS DAC f = 100 MHz OUT f = 350 MHz OUT f = 550 MHz OUT f = 950 MHz OUT Min 2.0 −10 −10 2 mA. FS Rev Page AD9739 Typ Max Unit 3 0.8 V +10 μA +10 μA 3 Min Typ Max Unit 800 2500 ...
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... AD9739 Parameter NOISE SPECTRAL DENSITY (NSD) Single Tone 2400 MSPS DAC f = 100 MHz OUT f = 350MHz OUT f = 550 MHz OUT f = 850 MHz OUT Eight-Tone 2400 MSPS, 500 kHz Tone Spacing DAC f = 100 MHz OUT f = 350 MHz OUT f = 550 MHz OUT f = 850 MHz ...
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... THERMAL RESISTANCE θ is specified for the worst-case conditions, that is, a device JA soldered in a circuit board for surface-mount packages. Table 5. Thermal Resistance Package Type 160-Ball CSP_BGA 1 With no airflow movement. ESD CAUTION Rev Page AD9739 θ θ Unit 31.2 7.0 °C/W ...
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... AD9739 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VDDA, 3.3V, ANALOG SUPPLY VSSA, ANALOG SUPPLY GROUND VSSA SHIELD, ANALOG SUPPLY GROUND SHIELD Figure 2. Analog Supply Pins (Top View VDD, 1.8V, DIGITAL SUPPLY VSS DIGITAL SUPPLY GROUND VDD33, 3.3V DIGITAL SUPPLY Figure 3. Digital Supply Pins (Top View) ...
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... Table 6. AD9739 Pin Function Descriptions Pin No. C1, C2, D1, D2, E1, E2, E3, E4 A1, A2, A3, A4, A5, B1, B2, B3, B4, B5, C4, C5, D4, D5 A10, A11, B10, B11, C10, C11, D10, D11 A12, A13, B12, B13, C12, C13, D12, D13, A6, A9, B6, B9, C6, C9, D6, D9, F1, F2, F3, F4, E11, E12, E13, E14, F11, F12 ...
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... AD9739 Pin No. L1, M1 L2, M2 L3, M3 L4, M4 L5, M5 L6, M6 L7, M7 L8, M8 L9, M9 L10, M10 L11, M11 L12, M12 L13, M13 L14, M14 N1, P1 N2, P2 N3, P3 N4, P4 N5, P5 N6, P6 N7, P7 N8, P8 N9, P9 N10, P10 N11, P11 N12, P12 N13, P13 N14, P14 1 Conforms to IEEE-1596 reduced range link. ...
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... Figure 11. Typical INL 85°C 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0 2048 4096 6144 Figure 12. Typical DNL 85°C Rev Page AD9739 8192 10,240 12,288 14,336 16,384 CODE 8192 10,240 12,288 14,336 16,384 CODE 8192 10,240 12,288 14,336 16,384 CODE ...
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... AD9739 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –2.5 –3.0 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 CODE Figure 13. Typical INL 25°C 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –2.5 –3.0 0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 CODE Figure 14. Typical DNL 25° ...
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... OUT WRT DIGFS @ 2.0 GSPS OUT –6dBFS –3dBFS 0dBFS 0 100 200 300 400 500 600 700 800 f (MHz) OUT WRT DIGFS @ 2.0 GSPS OUT AD9739 900 1000 900 1000 900 1000 ...
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... AD9739 90 80 10mA 20mA 100 200 300 400 500 600 f (MHz) OUT Figure 24. SFDR vs. f over ANAFS @ 2.0 GSPS OUT –40°C 60 +25° 100 200 300 400 500 600 f (MHz) OUT Figure 25. SFDR vs. f over Temperature @ 2.0 GSPS OUT 100 95 1 ...
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... OUT over Temperature @ 2.0 GSPS OUT FIRST ADJ CH SECOND ADJ CH FIFTH ADJ CH 245.76 491.52 737.28 983.04 122.88 368.64 614.40 860.16 1105.90 f (MHz) OUT @ 2457.6 MSPS OUT AD9739 900 1000 1228.80 ...
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... AD9739 CENTER 350.27MHz #RES BW 30kHz SWEEP 174.6ms (601pts) VBW 300kHz FREQ REF RMS RESULTS OFFSET BW LOWER (MHz) (MHz) (dBc) (dBm) CARRIER POWER 5 3.84 –79.90 –94.44 –14.54dBm/ 10 3.84 –80.60 –95.14 3.84MHz 15 3.84 –80.90 –95.45 20 3.84 –80.62 –95.16 25 3.84 –80.76 –95.30 Figure 35. Typical Single-Carrier WCDMA ACLR Performance @ 350 MHz f = 2457 ...
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... CARRIER POWER 5 3.84 –68.99 –90.43 –63.94 –21.43dBm/ 10 3.84 –72.09 –93.52 –71.07 3.84MHz 15 3.84 –72.86 –94.30 –71.34 20 3.84 –74.34 –95.77 –72.60 25 3.84 –74.77 –96.20 –73. 2457.6 MSPS (Second Nyquist Zone) DAC AD9739 @ 2457.6 MSPS (dBm) –90.37 –92.50 –92.77 –94.03 –94.70 ...
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... AD9739 CENTER 2.807GHz #RES BW 30kHz SWEEP 174.6ms (601pts) VBW 300kHz FREQ REF RMS RESULTS OFFSET BW LOWER (MHz) (MHz) (dBc) (dBm) CARRIER POWER 5 3.84 –64.90 –89.30 –24.4dBm/ 10 3.84 –66.27 –90.67 3.84MHz 15 3.84 –68.44 –92.84 20 3.84 –70.20 –94.60 25 3.84 –70.85 –95.25 Figure 43. Typical Single-Carrier WCDMA ACLR Performance @ 2.8 GHz 2457 ...
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... REF RMS RESULTS OFFSET BW LOWER UPPER CARRIER POWER (MHz) (MHz) (dBc) (dBm) (dBc) (dBm) 3.375 750 –72.35 –89.41 –72.58 –89.64 –17.06dBm/ 6.375 5.25 –76.50 –93.56 –77.89 –94.95 6MHz 12.00 6 –79.37 –96.43 –79.00 –96.06 18.00 6 –79.38 –96.45 –79.04 –96.10 AD9739 900 1000 ...
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... AD9739 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 0 100 200 300 400 500 600 f (MHz) OUT Figure 52. Single-Carrier DOCSIS ACLR Spectral Plot @ 825 MHz (DOCSIS SPEC (Red Line dBc ; Harmonic Exception Is 63 dBc) CENTER 817.2MHz #RES BW 30kHz VBW 300kHz ...
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... AD9739 800 900 1000 SPAN 18MHz (dBm) –99.83 –95.78 SPAN 42MHz (dBm) –100.47 –95.57 –94.71 –94.76 ...
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... AD9739 0 –10 –20 –30 –40 –50 –60 –70 –80 0 100 200 300 400 500 600 F (MHz) OUT Figure 64. Eight-Carrier DOCSIS ACLR Spectral Plot @ 100 MHz (DOCSIS SPEC (Red Line dBc; Harmonic Exception Is 54 dBc) 0 –10 –20 –30 –40 –50 –60 –70 – ...
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... Figure 72. 72-Carrier DOCSIS ACLR Spectral Plot @ 700 MHz (DOCSIS SPEC (Red Line dBc; Harmonic Exception Is 35 dBc) 800 900 1000 Rev Page AD9739 100 200 300 400 500 600 700 800 900 f (MHz) OUT 1000 ...
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... AD9739 TERMINOLOGY Linearity Error (Integral Nonlinearity or INL) The maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. Differential Nonlinearity (DNL) The measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. ...
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... THEORY OF OPERATION The AD9739 is a 14-bit DAC that operates at an update rate 2.5 GSPS. Due to internal timing requirements, the minimum allowable sample rate is 800 MSPS. Input data is sampled through two 14-bit LVDS ports that are internally multiplexed. Each port has its own data inputs, but both ports share a common DCI input ...
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... SDIO After the last instruction bit is written to the SDIO pin, the driving signal must be set to a high impedance in time for the bus to turn around. The serial output data from the AD9739 is enabled by the falling edge of SCLK. This causes the first output D5 ...
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... DCI_DEL[6] DCI_DEL[5] DCI_DEL[4] FINE_DEL_ FINE_DEL_ FINE_DEL_ FINE_DEL_ PST[1] PST[0] PRE[3] PRE[2] SYNCO_ SYNCO_ SYNCO_ SYNCO_ DEL[5] DEL[4] DEL[3] DEL[2] Rev Page AD9739 Bit 1 Bit 0 Default N/A N/A 0x00 CLK_REC_ DAC_BIAS 0x00 PD _PD REC_CNT_ MU_CNT_ 0x03 CLK CLK RCV_ RCV_ 0x00 LST_EN ...
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... AD9739 Name Address Bit 7 Bit 6 LVDS_ 0x1F SYNCSH_ N/A DEL[0] REC_STAT7 LVDS_ 0x20 SYNCSH_ SYNCSH_ DEL[8] DEL[7] REC_STAT8 LVDS_ 0x21 SYNC_TRK SYNC_INIT _ON _ON REC_STAT9 CROSS_ 0x22 N/A N/A CNT1 CROSS_ 0x23 N/A N/A CNT2 PHS_DET 0x24 N/A N/A MU_DUTY 0x25 ...
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... DAC bias circuitry powered down. Bit 6 Bit 5 Bit 4 Bit 3 N/A N/A N/A CLKGEN_PD Bit 5 Bit 4 Bit 3 SYNC_LST_EN SYNC_LCK_EN MULST_EN SYNC_LST_IRQ SYNC_LCK_IRQ MULST_IRQ Rev Page AD9739 Reset Value for Write Register Bit 2 Bit 1 Bit 0 N/A REC_CNT_CLK MU_CNT_CLK Reset Value for Write Register Bit 2 ...
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... AD9739 Bit Name Read/Write Description MULCK_IRQ Read 0: the mu controller is unlocked. 1: the mu controller has achieved lock and an interrupt has occurred. RCVLST_IRQ Read 0: the RCV controller has not lost lock. 1: the RCV controller has lost lock and an interrupt has occurred. RCVLCK_IRQ Read 0: the RCV controller is unlocked. ...
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... One or more LVDS inputs on Port 0 are above the input voltage limits of the IEEE reduce link specification. LVDS0_LO Read One or more LVDS inputs on Port 0 are below the input voltage limits of the IEEE reduce link specification. Rev Page AD9739 Reset Value for Write Register 0x00 0x0 0 0 ...
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... AD9739 Table 22. LVDS Receiver Control Registers (Register 0x10, Register 0x11, Register 0x12, Register 0x13, Register 0x14, Register 0x15, Register 0x16, Register 0x17, Register 0x18) Register 1 Name Address Bit 7 LVDS_ 0x10 16 SYNC_ FLG_RST REC_CNT1 LVDS_ 0x11 17 SMP_DEL[1] REC_CNT2 LVDS_ 0x12 18 SMP_DEL[9] REC_CNT3 ...
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... SYNCO_ SYNCO_ SYNCO_ DEL[3] DEL[2] DEL[1] N/A N/A N/A SYNCSH_ SYNCSH_ SYNCSH_ DEL[4] DEL[3] DEL[2] RCVR_TRK_ RCVR_FE_ RCVR_LST_ ON ON LCK Reset Value for Write Register AD9739 Bit 0 SMP_FINE _DEL[0] SMP_DEL[2] CLKDIV PH[0] DCI_DEL[2] FINE_DEL_ PRE[0] SYNCO_ DEL[0] N/A SYNCSH_ DEL[1] RCVR_LCK ...
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... AD9739 Bit Name Read/Write Description RCVR_FE_ON Read 0: indicates that the FINDEDGE state machine is not active. 1: indicates that the FINDEDGE state machine is active. RCVR_LST_LCK Read 0: lock has not been lost. 1: lock has been lost at some point. RCVR_LCK Read 0: the receiver controller is not locked. ...
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... GB (optimal value is Decimal 11 or 0x0B). ContRst Read/write Controls whether the controller resets or continues if it does not find the desired phase. 0x0: continue (optimal setting). 0x1: reset. Rev Page AD9739 Reset Value for Write Register ...
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... AD9739 Bit Name Read/Write Description Retry Read/write 0x0: if the correct value is not found, the search stops. 0x1: if the correct value is not found, the search begins again. Search_Tol Read/write 0x0: not exact (can find a phase within two values of the desired phase). 0x1: finds the exact phase that is targeted (optimal setting). ...
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... ZERO MODE OUT This ability to change modes in the AD9739 makes it suitable for both CMTS and UMTS applications. The user can place a carrier anywhere in the first three Nyquist zones, depending on the operating mode selected. Switching between the analog modes reshapes the sinc roll-off inherent at the DAC output. ...
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... AD9739 The SYNC_IN_x and SYNC_OUT_x signals are used to synchronize multiple parts (see the Synchronization Controller section for more information). Each data port runs internally at half the speed of the DACCLK_x, and the two ports are subse- quently multiplexed together to achieve the full DAC update rate. ...
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... CLOCKING THE AD9739 To provide the required signal swing for the internal clock receiver of the AD9739 necessary to use an external clock buffer chip to drive the DACCLK_P and DACCLK_N inputs. The recommended clock buffer for this application is the ADCLK914. This is an ultrafast clock buffer capable of providing 1.9 V out of each side into a 50 Ω ...
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... DEINTERLEAVE DB2 FILE DB3 DB4 DB5 Figure 87. Graphical Representation of How to Present Data to the AD9739 To still meet the close-in ACLR requirements for the eight- carrier DOCSIS, the phase noise found in Profile 3 is the ADCLK914 minimum requirement necessary. APPLYING DATA TO THE AD9739 As explained in the LVDS Data Port Interface section, each data ...
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... Reset (0x1) phase is measured, Rev Page used to specify the accuracy of the search 18 16 GUARD 14 BAND 12 10 DESIRED PHASE SEARCH STARTING 2 LOCATION 120 160 200 240 280 320 MU DELAY Figure 89. Typical Mu Phase Characteristic Plot @ 2.4 GSPS AD9739 GUARD BAND 360 400 440 ...
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... AD9739 To determine the correct slope, the controller measures the slope by first incrementing and then decrementing the mu delay value until any of the following happens: • The phase changes by 2. • The phase is equal to 16 (the maximum value). • The phase is equal to 0 (the minimum value). ...
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... SYNC_IN_x position across temperature. FF DCI WINDOW SAMPLE DCI WINDOW POST FF DCI WINDOW PRE SYNC_DEL FF C1_DEL C0_DEL CONTROLLER FF SO DELAY SO SELECT DELAY SYNC_TRACK DELAY DELAY SYNC_OUT DELAY Rev Page AD9739 PHASE DAC 2 /4 CLOCK ...
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... AD9739 Operation in Master Mode Setting Register 0x10, Bit 5 high sets the controller to master mode. This enables the sync logic to enter an initialization phase that adjusts the SYNC_OUT_x delay. By moving the SYNC_OUT_x delay, the SYNC_IN_x sampling point is moved and the edge transitions of Phase 0 and Phase 1 clocks can be determined ...
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... The data receiver controller can be set up to loop when an error occurs by setting the RCVR_LOOP_ON bit in the SPI (Register 0x10, Bit 1). If this bit is set, the controller generates an IRQ and restart, beginning with the clock phase determination, followed Rev Page AD9739 PHASE 0 2 DAC ...
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... AD9739 by the DCI transition detection, and then back into track mode. Status bits are available in the SPI to verify that the receiver controller has found lock (Register 0x21, Bit 0), that the receiver controller has entered tracking mode (Register 0x21, Bit 3), and whether the controller has lost lock (Register 0x21, Bit 1). ...
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... VOLTAGE REFERENCE The AD9739 output current is set by a combination of digital control bits and the I120 reference current, as shown in Figure 102. CLKP CLKN The reference current is obtained by forcing the band gap voltage across an external 10 kΩ resistor from I120 (Pin B14) to ground. The 1.2 V nominal band gap voltage (VREF) generates a 120 μ ...
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... Figure 103. IFS vs. DAC Gain Code Always connect a 10 kΩ resistor from the I120 pin to ground and use the digital controls to vary the full-scale current. The AD9739 is not a multiplying DAC. Applying an analog signal to I120 is not supported. VREF (Pin C14) must be bypassed to ground with capacitor ...
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... The differential voltage existing between IOUTP and IOUTN can also be converted to a single-ended voltage via a transformer or differential amplifier configuration. Internal to the AD9739 is a differential resistance between IOUTP and IOUTN that must be factored into the calculations for the voltage output and impedance out of the DAC. The approximate impedance between the outputs is 70 Ω ...
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... AD9739 RECOMMENDED START-UP SEQUENCE The steps necessary to optimize the performance of the part and generate an output waveform are as follows: 1. Enable clocks to the controller and set the full-scale current. The registers and bits used in this step are shown in Table 35. Recommended values for the bits are in parentheses. ...
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... Bit 5 Bit 4 Bit 3 Bit 2 SYNC_ SYNC_ N/A RCVR_ CNT_ENA FLG_RST MST/SLV (1) (0) (0) SYNCOUT_ SYNCOUT_ LCKTHR[3] LCKTHR[2] PH[1](0) PH[0](0) (0) (0) Rev Page AD9739 Recommended Bit 2 Bit 1 Bit 0 Value Bias[2] Bias[1] Bias[0] 0x30 (0) (0) (0) ADJ[2] ADJ[1] ADJ[0] 0x80 (0) (0) (0) Gain[1] Gain[0] Enable (1) 0x03 ...
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... AD9739 To verify that the sync controller is locked and tracking, the following bits must be read back: • Register 0x21, Bit 4 (SYNC_LCK)—If the controller is locked, this bit reads back a value of 1. This is a value of 1 for the master part only. If the part is set slave, this bit reads back 0. ...
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... MAX ORDERING GUIDE Model Temperature Range 1 AD9739BBCZ −40°C to +85°C 1 AD9739BBCZRL −40°C to +85°C AD9739BBC −40°C to +85°C AD9739BBCRL −40°C to +85°C 1 AD9739-EBZ 1 AD9739-MIX-EBZ 1 AD9739-CMTS-EBZ RoHs Compliant Part. 12.10 12. 11. BALL A1 INDICATOR 10.40 TOP VIEW BSC SQ ...
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... AD9739 NOTES Rev Page ...
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... NOTES Rev Page AD9739 ...
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... AD9739 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07851-0-1/09(0) Rev Page ...