AD9739BBCRL Analog Devices Inc, AD9739BBCRL Datasheet - Page 40

• Manufacturer Part Number: AD9739BBCRL
• Description: 14 Bit 2.5 GSPS DAC
• Manufacturer: Analog Devices Inc

Specifications of AD9739BBCRL

• Number Of Bits: 14
• Data Interface: Serial
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 980mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 160-CSPBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Settling Time: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD9739
Clock Phase Noise Affects on AC Performance
The quality of the clock source driving the
determines the achievable ACLR performance for the AD9739.
Table 32 summarizes the close-in ACLR for an eight-carrier
DOCSIS signal at 920 MHz with respect to various phase noise
profiles.
Table 32. Eight-Carrier DOCSIS Close-In ACLR
Performance at 920 MHz for Various Phase Noise Profiles
Band
750 kHz
to 6 MHz
6 MHz to
12 MHz
12 MHz
to 18
1
Table 33 shows the phase noise at various offsets for each profile.
Table 33. Phase Noise Summary for Each Profile
Offset
1 kHz
10 kHz
100 kHz
1 MHz
10 MHz
100 MHz
1
All ACLR numbers are specified in decibels relative to the carrier (dBc).
All phase noise numbers are specified in dBc/Hz.
MHz
Phase
Noise
Profile 1
−68.5
−68
−68
−141.2
−150.4
−150.4
Profile 1
−111.3
−117.4
−123.7
ORIGINAL
DATA
DB0
DB1
DB2
DB3
DB4
DB5
FILE
DEINTERLEAVE
FILE
Phase
Noise
Profile 2
−65
−66.5
−67.5
Profile 2
−109.3
−115.9
−120.3
−125.8
−147.2
−150.3
Phase
Noise
Profile 3
−61.1
−64
−67.3
Figure 87. Graphical Representation of How to Present Data to the AD9739
DB0[13:0]N
DB1[13:0]N
DB0[13:0]P
DB1[13:0]P
Profile 3
−109.25
−114.6
−117.3
−122
−124.6
−150.6
ADCLK914
Phase
Noise
Profile 4
−56
−60
−67.6
1
DB0, DB2, DB4...
DB1, DB3, DB5...
Profile 4
−107.5
−114
−114.4
−115.6
−117.9
−150.6
Spec
−59.3
−61.8
−64
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To still meet the close-in ACLR requirements for the eight-
carrier DOCSIS, the phase noise found in Profile 3 is the
minimum requirement necessary.
APPLYING DATA TO THE AD9739
As explained in the LVDS Data Port Interface section, each data
port runs internally at half the speed of the DACCLK_x, and
the two ports are subsequently multiplexed together to achieve
the full DAC update rate. If the user is creating a data file to
load into the AD9739, this data file must be deinterleaved and
applied to each port, as shown in Table 34.
Table 34. Application of Deinterleaved Files to Ports
Original Data File
DB0
DB1
DB2
DB3
DB4
DB5
A graphical representation of this can be seen in Figure 87. If
the data pattern generator (DPG2) is being used to apply data to
the part, the deinterleaving process can be done automatically
via the software. Thus, the user can apply a single data file using
the DPG2 and allow the software to do the deinterleaving and
apply the correct data to each port.
DB0, DB1, DB2,
DB3, DB4...
Apply to DB0[13:0]
Yes
No
Yes
No
Yes
No
14-BIT, 12-BIT,
10-BIT DAC
CORE
IOUTP
IOUTN
Apply to DB1[13:0]
No
Yes
No
Yes
No
Yes