AD9739BBCZRL Analog Devices Inc, AD9739BBCZRL Datasheet - Page 42

• Manufacturer Part Number: AD9739BBCZRL
• Description: 14 Bit 2.5 GSPS DAC
• Manufacturer: Analog Devices Inc

Specifications of AD9739BBCZRL

• Number Of Bits: 14
• Data Interface: Serial
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 980mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 160-CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9739
To determine the correct slope, the controller measures the
slope by first incrementing and then decrementing the mu delay
value until any of the following happens:
•
•
•
•
•
After both incrementing and then decrementing the mu delay
value, the values of the measured phases are compared to
determine if the slope matches the desired slope. To consider
the slope valid, the positive direction phase and the negative
direction phase must be on opposite sides of the desired phase.
Figure 90 and Figure 91 contain examples of valid and invalid
phase choice.
Track Mode
In tracking mode, a simple control loop is used to increment by
1, decrement by 1, or not change the mu delay value, depending
on the measured phase. The control loop uses the desired slope
to determine if the mu delay should be incremented or decre-
mented. No attempt is made to determine if the actual slope has
changed or is still valid.
Two status bits, MU_LKD (Register 0x2A, Bit 0) and
MU_LOST (Register 0x2A, Bit 1) are available to the user to
signal proper operation of the control loop. If the current phase
is more than five steps away from the desired phase, the
MU_LKD bit is cleared, and the MU_LOST bit is set if the lock
acquired was previously set. Furthermore, if lock is lost, the
controller has the option of remaining in the tracking loop or
resetting and starting the search again.
PO
SL
10
SITIVE
11
OPE
The phase changes by 2.
The phase is equal to 16 (the maximum value).
The phase is equal to 0 (the minimum value).
The mu delay is 431 (the maximum value).
The mu delay is 0 (the minimum value).
12
12
13
Figure 90. Valid Positive and Negative Slope Phase Examples
14
13
DESIRED
15
DESIRED
14
Figure 91. Invalid Slope Phase Examples
15
15
14
13
4
3
2
1
DESIRED
DESIRED
9
1
8
NEGATIVE
SLOPE
2
7
3
6
5
4
Rev. 0 | Page 42 of 56
Mu Delay and Phase Readback
By setting the read bit high (Register 0x26, Bit 3), the user can
read back the mu delay value that the controller locked to by
reading the MUDEL[8:0] bits and the phase it locked to by
reading back the SetPhs[4:0] bits. These no longer read back the
value the search started at or the desired phase. The MUDEL[8:0]
bits should now read back the mu delay line value the controller
locked to and the phase it locked to. The typical locking time
for the mu controller is approximately 180 K DAC cycles (at
2 GSPS ~ 75 μs).
Operating the Mu Controller Manually
To manually control the mu delay, the user must sweep through
all of the mu delay values and the record phase value at each
value of MUDEL, as shown in Figure 89. In manual mode, it is
recommended to enable the phase comparator boost (Register
0x24, Bits[5:4]) and the mu delay controller duty cycle correction
circuitry (Register 0x25, Bit 7). Every time the MUDEL value is
stepped, the read bit must be set high to read the corresponding
phase for the specified mu delay line value. It is not possible to
keep the read bit high and continuously read back the phase
value. As is the case with auto mode, the optimal ac performance
occurs at a negative slope and a phase of 6; therefore, when the
curve is complete, choose the MUDEL value that corresponds
to this condition and write that value into the MUDEL[8:0] bits.
Instead of manually sweeping through all of the mu delay
values, it is possible to set the Mode[1:0] bits to 0x2 and search
only for the mu delay value for the specified phase. In this case,
the mu enable bit must be set high to perform the search.
The user then needs to occasionally monitor the phase and
make adjustments to maintain an optimal phase relationship.
Another option is to set the Mode[1:0] bits to 0x1 to allow the
controller to track only from the specified mu delay value. In
this case, the mu enable bit must be set high to perform the
tracking.
Calculating Mu Delay Line Step Size
Stepping through all of the mu delay line values and plotting
mu phase vs. mu delay not only allows the user to find the
optimal mu delay value but also allows the user to determine
the mu delay line step size. To calculate the step size, take one
full cycle of the mu phase curve and divide the period of the
DAC clock by this delta. From Figure 89, the two transition
points are approximately 56 and 270, providing a delta of
approximately 214 steps. Therefore, the mu delay line step size is
Or approximately 2 ps/step. If the mu delay controller is
enabled, this value allows the user to calculate how much drift is
in their system (in picoseconds) with respect to the DAC clock
period over temperature.
2
4 .
24
1
e
9
=
. 1
95
ps