AD9739BBCZRL Analog Devices Inc, AD9739BBCZRL Datasheet - Page 46

• Manufacturer Part Number: AD9739BBCZRL
• Description: 14 Bit 2.5 GSPS DAC
• Manufacturer: Analog Devices Inc

Specifications of AD9739BBCZRL

• Number Of Bits: 14
• Data Interface: Serial
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 980mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 160-CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9739
by the DCI transition detection, and then back into track mode.
Status bits are available in the SPI to verify that the receiver
controller has found lock (Register 0x21, Bit 0), that the receiver
controller has entered tracking mode (Register 0x21, Bit 3), and
whether the controller has lost lock (Register 0x21, Bit 1).
With the synchronization controller off or with the part in slave
mode, the LVDS controller typically locks in 70 K DAC cycles
(at 2 GSPS ~ 35 μs). The worst-case locking time is 135 K DAC
cycles (at 2 GSPS ~ 67.5 μs). With the synchronization controller
on and the part in master mode, the LVDS controller typically
locks in 301 K DAC cycles (at 2 GSPS ~ 150 μs). The worst-case
locking time is 555 K DAC cycles (at 2 GSPS ~ 277.5 μs).
DBx[13:0]
DATA RECEIVER OPERATION IN MANUAL MODE
If the receiver controller is disabled, the timing adjustments can
be done manually. The user must adjust the DCI_DEL bits in
Register 0x13 and Register 0x14 and monitor the DCI_PRE_
PH0 bit (Register 0x0C, Bit 2) or the DCI_PST_PH0 bit
(Register 0x0C, Bit 0) to determine where the DCI rising edge
occurs. If there is no skew programmed in the FINE_DEL_SKW
bits, then both the DCI_PRE_PH0 bit and the DCI_PST_PH0
bit transition at the same time. When the delay setting is found,
the optimal value must be written to the DCI_DEL bits. This
same delay value also must be applied to the SMP_DEL bits
(Register 0x11 and Register 0x12) to set the proper sampling
point for the Phase 1 clock, which is used to sample the
incoming data into the DAC core.
Because the controller is off, there is no tracking of the DCI_x
signal; therefore, the user must monitor the DCI_PST_PH0 and
DCI_PRE_PH0 bits periodically to determine if the timing has
shifted due to temperature or other causes. In addition to
monitoring these bits, it is also important to ensure that the
handoff timing between the flip flops in the data path is valid.
As shown in Figure 84, the optimal sample delay value is split
PHASE 0
PHASE 1
PHASE 2
PHASE 3
Figure 97. Phase Relationship of Clocks During Locked Receiver State
DCI
800ps AT 2.5GHz
MIN. PERIOD
Rev. 0 | Page 46 of 56
between these flip flops in the data path. If the timing in any
one of these stages is violated, one of the status bits in Register
0x0B (HNDOFF_Fall[3:0] or HNDOFF_Rise[3:0]) reads back a
value of 1. If this occurs, it is necessary to adjust the sample
delay and, in turn, the DCI delay so as to not violate the timing
between these flip flops. When the new sample delay value is
found, the HNDOFF check bits can be reset by setting the
HNDOFF_CHK_RST bit high (Register 0x0A, Bit 3).
Calculating the DCI Delay Line Step Size
To calculate the DCI delay line step size, the user must step
through all the values of the DCI delay line manually and
record the state of DCI_PRE_PH0. A typical plot of this
measurement at 2.4 GSPS is shown in Figure 98
To calculate the step size, take the transition points of the Phase 0
state curve and divide the period of the DCI clock (1/2 of the
DAC clock rate) by this delta. As shown in Figure 98, two trans-
ition points are approximately 26 and 97, providing a delta of
approximately 71 steps. Therefore, the DCI delay line step size is
Or approximately 12 ps/step.
MAXIMUM ALLOWABLE DATA TIMING
SKEW/JITTER
The maximum allowable skew and jitter out of an FPGA with
respect to the DDR DCI clock edge on each LVDS port is
calculated as
The minimum LVDS valid window is approximately 344 ps,
as shown in Table 2, and a guard of 100 ps is recommended.
Therefore, at the maximum operating frequency of 2.5 GSPS,
the maximum allowable FPGA skew plus jitter is equal to
MaxSkew + Jitter =
1
2 .
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
71
Period(ns) – ValidWindow(ps) − Guard
1
0
e
0
9
Figure 98. DCI Delay Line Step Size Measurement
=
11
.
65
DCI DELAY CHARACTERIZATION AT 2.4GSPS
ps
100
DCI DELAY
200
300
400