AD9765-EBZ Analog Devices Inc, AD9765-EBZ Datasheet - Page 3

• Manufacturer Part Number: AD9765-EBZ
• Description: 12-Bit, 125 MSPS DUal TxDAC+
• Manufacturer: Analog Devices Inc
• Series: TxDAC+®r

Specifications of AD9765-EBZ

• Number Of Dac's: 2
• Number Of Bits: 12
• Outputs And Type: 2, Differential
• Sampling Rate (per Second): 125M
• Data Interface: Parallel
• Settling Time: 35ns
• Dac Type: Current
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9765
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DUAL DAC MODE
Jumper J8 controls the logic level of the MODE pin on
the AD976x dual DAC. With this jumper in the D posi-
tion, the mode pin is pulled to a high logic level and the
AD976x is in dual DAC mode.
The simplest method for operating the dual DAC evalua-
tion board in the dual DAC mode is to select a common
clock for WRT1, WRT2, CLK1, and CLK2. An external
clock generator can be selected by inserting JP16, or a
clock from the word generator can be selected by insert-
ing JP9. By inserting JP3, JP4, and JP5 all in the C position,
the selected clock can be applied to all four clock inputs.
Different combinations of JP3, JP4, and JP5 allow
multiple options if the user desires to drive the WRT
and CLK inputs from separate clocks.
In the dual mode, jumpers JP1 and JP2 should be
removed. The state of Jumpers JP6 and JP7 does not
matter in this mode.
Table I illustrates the jumper positions required to oper-
ate in the dual DAC mode of operation.
Jumper
JP1, JP2,
JP6, JP7
JP3, JP4,
JP5
JP8
JP9
JP16
INTERLEAVING MODE
With jumper JP8 in the I position, the MODE pin on the
AD976x is pulled to a logic low level and the DAC is in
interleaving mode. In this mode, a single stream of digi-
tal data drives Port 1 on the DAC. This stream of data
contains alternating bits from two data channels. By
using the correct clock and control signals, data in the
two channels will be separated and sent to the correct
DAC outputs. This is typical of an I/Q application.
In interleaving mode, the definitions for the four clock
inputs change. WRT1, WRT2, CLK1, and CLK2 become
IQWRT, IQCLK, IQRESET, and IQSEL, respectively. For
REV. 0
Table I. Jumper Options for Dual DAC Mode
Position
Removed
C
D
Optional
Optional
Description
These are only used in
interleaved mode.
With these in the B posi-
tion, the evaluation board
can be run with one com-
mon clock.
Enables Dual DAC Mode.
Selects clock from word
generator. Remove JP9 if
clock source is from S1/JP16.
Selects clock from connec-
tor S1. Remove JP16 if clock
source is from JP9/JP16/
DCLK1, DCLK2.
–3–
detailed information on the functions of these inputs, as
well as the DAC input and output timing, see the
AD9709, AD9763, AD9765, and AD9767 data sheets.
Operation with a single clock can be achieved by select-
ing JP16 or JP9 for the clock source and inserting JP5 in
the C position, and removing JP3. JP4 can be used to
control IQRESET, but for most evaluations can simply be
tied low (Position I).
In interleaving mode, digital data present at input Port 1
is written into the Port 1 or Port 2 input buffers internal
to the DAC on the rising edge of IQWRT. The port into
which data is written depends on the state of IQSEL at the
time of the IQWRT rising edge. If IQSEL is high when the
rising edge occurs, data will be written to input Port 1. If
IQSEL is low at that time, data will be written to input
Port 2.
U1 on the evaluation board provides an alternating
IQSEL signal by toggling on every falling edge of
IQWRT. To enable this function, insert JP1 and JP2 and
remove JP3. JP6 and JP7 are used to synchronize the
input data stream with the IQSEL pin. To perform this
synchronization, power up the evaluation board with the
IQWRT and input data clocks disabled and at logic low. If
the first word in the digital data stream is meant for
Channel 1, preset U1 by inserting JP7 in the H position,
temporarily insert JP6 in the L position, then permanently
in the H position. If the first word in the data stream in
intended for Channel 2, reset U1 by inserting JP6 in the
H position, insert JP7 temporarily in the L position, then
permanently in the H position.
Table II illustrates the jumper positions required to oper-
ate in the dual DAC mode of operation.
Jumper
JP1, JP2
JP3
JP4
JP5
JP6, JP7
JP8
JP9
JP16
Table II. Jumper Options for Interleaved Mode
Position
Inserted
Remove
I
C
I
Optional
Optional
Description
These enable U1 to generate the
alternating logic signal for IQSEL.
If the IQSEL logic is to be gener-
ated by U1, this is not needed.
Use to allow S3 control of
IQRESET pin.
Allows IQWRT and IQCLK to be
driven by a common clock.
These are used to preset the
IQSEL pin before the data clock
is enabled. See text for descrip-
tion of use.
Enables Interleaved Mode.
Selects clock from word genera-
tor. Remove JP9 if clock source
is from S1/JP16.
Selects clock from Connector S1.
Remove JP16 if clock source is
from JP9/DCLK1, DCLK2.
AN-555