AD9765-EBZ Analog Devices Inc, AD9765-EBZ Datasheet - Page 4

• Manufacturer Part Number: AD9765-EBZ
• Description: 12-Bit, 125 MSPS DUal TxDAC+
• Manufacturer: Analog Devices Inc
• Series: TxDAC+®r

Specifications of AD9765-EBZ

• Number Of Dac's: 2
• Number Of Bits: 12
• Outputs And Type: 2, Differential
• Sampling Rate (per Second): 125M
• Data Interface: Parallel
• Settling Time: 35ns
• Dac Type: Current
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9765
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AN-555
CLOCK TIMING/PERFORMANCE
To ensure that specified setup-and-hold times are met,
the digital data inputs should change state on the falling
edge of the clock. However, due to timing skews and
delays inherent in some circuits, this does not always
happen. If the timing of the data transition and the rising
edge of the clock violates the setup-and-hold times, SNR
performance will be seriously degraded. Figure 5 shows
the valid window during the clock cycle in which the
digital input data can transition with no degradation in
SNR performance.
Correct timing can be verified by generating a word pat-
tern that repeatedly toggles the LSBs between Logic 1
and Logic 0. The user will also need a digital oscillo-
scope with persistence capability.
Place one probe from the scope on the clock input of the
DAC. The sensitivity of this measurement is in the tenths
of nanoseconds, so the probe should be placed as close
as possible to the DAC itself. In addition, the scope
should be set to trigger from this channel. Place a second
probe from the oscilloscope on the LSB input of the
DAC, again as close as possible to the DAC itself. The
barrels of both probes should be grounded to the
evaluation board, as close to the measurement point as
possible. A convenient way of doing this is to wrap a
piece of bus wire around the barrel and then solder the
other end of the bus wire to the PCB. Figure 6 illustrates
a typical oscilloscope display for this test, as well as the
proper way to use the scope probes.
For the most accurate results, identical high input
impedance, low input capacitance probes should be
used. If possible, they should also be calibrated.
The data setup time can be measured by placing a vari-
able delay between the clock generator and the clock
input of the word generator. This is most often done by
using a pulse generator. By adjusting the delay of the
digital data, place the data transition point on the falling
edge of the clock. At this point, SNR should be opti-
mized. Increase the amount of delay for the digital data,
moving the transition point closer to the rising edge. As
the data transition gets close to the rising edge, SNR will
begin to degrade. At this point, on the oscilloscope,
measure the time difference between the data transition
and the midpoint of the rising edge. This is the mea-
sured data setup time.
Figure 5. Valid Window for Data Transition During
Clock Cycle
CLOCK
DATA
t
S
t
H
–4–
To measure the input data hold time, perform the same
operation, but start with the data transition occurring at
the midpoint of the clock transition. SNR at this point
will be completely degraded. Increase the digital input
delay until the SNR is optimized. At this point, again
measure the time difference between the data transition
and the midpoint of the rising edge. This is the mea-
sured data hold time.
REFERENCE OPERATION
The AD9709, AD9763, AD9765, AD9767 contain a single
1.2 V reference that is shared by both of the DACs on the
chip. This reference drives two control amplifiers that
independently control the full-scale output currents in
each of the two DACs. Using the 1.2 V reference and the
control amplifier, reference currents are produced for
each DAC in an external resistor attached to FSADJ1
(DAC1) and to FSADJ2 (DAC2). The relationship between
the external resistor current and the full-scale output
current is:
Using the internal reference, this can also be expressed
as:
On the evaluation board, R9 and R10 are the two exter-
nal resistors that define the full-scale current.
An external reference can also be used simply by driving
the REFIO pin on the dual DAC (TP36) with an external
reference. The input impedance of the REFIO pin is very
high, minimizing any loading of the external reference.
However, because some references behave poorly
when driving capacitive loads, the bypass capacitor on
Figure 6. Verifying Clock/Data Timing on Evaluation
Board, Proper Use of Scope Probes
CLOCK
DATA
CHANNEL 1
I
OUT
FS = 32
I
OUT
FS = 38.4
Reference Current
CHANNEL 2
R
EXT
REV. 0