AD9887AKSZ-140 Analog Devices Inc, AD9887AKSZ-140 Datasheet
AD9887AKSZ-140
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AD9887AKSZ-140 Summary of contents
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FEATURES Analog interface 170 MSPS maximum conversion rate Programmable analog bandwidth 0 1.0 V analog input range 500 ps p-p PLL clock jitter at 170 MSPS 3.3 V power supply Full sync processing Midscale clamping 4:2:2 output format ...
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AD9887A TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Analog Interface ........................................................................... 3 Digital Interface ............................................................................ 5 Absolute Maximum Ratings............................................................ 7 Explanation of Test Levels ...
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SPECIFICATIONS ANALOG INTERFACE 3.3 V, ADC clock = maximum conversion rate, unless otherwise noted Table 1. Test Parameter Temp Level RESOLUTION DC ACCURACY Differential Nonlinearity 25°C I Full VI Integral Nonlinearity 25°C ...
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AD9887A Test Parameter Temp Level DIGITAL INPUTS Voltage High, V Full VI IH Voltage Low, V Full VI IL Current High, V Full IV IH Current Low, V Full IV IL Capacitance 25°C V DIGITAL OUTPUTS Voltage High, V Full ...
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DIGITAL INTERFACE VD = 3.3 V, VDD = 3.3 V, clock = maximum, unless otherwise noted. Table 2. Parameter RESOLUTION DC DIGITAL I/O SPECIFICATIONS High Level Input Voltage Low Level Input Voltage High Level Output Voltage, ...
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AD9887A Parameter Low-to-High Transition Time (D ) for DATACK LHT High-to-Low Transition Time (D ) for Data HLT High-to-Low Transition Time (D ) for DATACK HLT 3 Clock-to-Data Skew, t SKEW 3 Duty Cycle, DATACK, DATACK DATACK Frequency (f ) ...
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ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Analog Inputs VREFIN Digital Inputs Digital Output Current Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Maximum Case Temperature Stresses above those listed under Absolute Maximum Ratings may cause ...
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AD9887A PIN CONFIGURATION AND FUNCTION DESCRIPTIONS GND PIN 1 2 IDENTIFIER GREEN A<7> 3 GREEN A<6> 4 GREEN A<5> 5 GREEN A<4> 6 GREEN A<3> 7 GREEN A<2> 8 GREEN A<1> 9 GREEN A<0> ...
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Table 4. Pin Function Descriptions Pin Type Mnemonic Analog Video Data Inputs R AIN G AIN B AIN Sync/Clock Inputs HSYNC VSYNC SOGIN CLAMP COAST CKEXT CKINV Sync Outputs HSOUT VSOUT SOGOUT Voltage References REFOUT REFIN Clamp Voltages R V ...
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AD9887A Pin Type Mnemonic 2-Wire Serial Interface SCL A0 A1 Data Outputs RED B[7:0] GREEN B[7:0] BLUE B[7:0] RED A[7:0] GREEN A[7:0] BLUE A[7:0] Data Clock Outputs DATACK DATACK Sync Detect S CDT Scan Function SCAN IN SCAN OUT SCAN ...
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PIN FUNCTION DETAILS—PINS SHARED BETWEEN DIGITAL AND ANALOG INTERFACES Sync Outputs HSOUT Horizontal Sync Output The horizontal sync output is a reconstructed version of the video Hsync, phase-aligned with DATACK. The polarity of this output can be controlled via a ...
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AD9887A Power Supplies V Main Power Supply D These pins supply power to the main elements of the circuit. They should be filtered quiet as possible. V Digital Output Power Supply DD These supply pins are identified ...
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PIN FUNCTION DETAILS—ANALOG INTERFACE Analog Video Data Inputs R Analog Input for Red Channel AIN G Analog Input for Green Channel AIN B Analog Input for Blue Channel AIN These are the high impedance inputs that accept graphics signals from ...
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AD9887A CKINV Sampling Clock Inversion (Optional) This pin can be used to invert the pixel sampling clock, which has the effect of shifting the sampling phase 180°. This supports the alternate pixel sampling mode, wherein higher frequency input signals (up ...
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R V Red Channel Midscale Clamp Voltage Output MIDSC G V Green Channel Midscale Clamp Voltage Output MIDSC B V Blue Channel Midscale Clamp Voltage Output MIDSC R V Red Channel Midscale Clamp Voltage Input CLAMP G V Green Channel ...
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AD9887A PIN FUNCTION DETAILS—DIGITAL INTERFACE Digital Video Data Inputs Rx0+ Digital Differential Input Channel 0 True Rx0− Digital Differential Input Channel 0 Complement Rx1+ Digital Differential Input Channel 1 True Rx1− Digital Differential Input Channel 1 Complement Rx2+ Digital Differential ...
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THEORY OF OPERATION AND DESIGN GUIDE—ANALOG INTERFACE GENERAL DESCRIPTION The AD9887A is a fully integrated solution for capturing analog RGB signals and digitizing them for display on flat panel monitors or projectors. The device is ideal for implementing a computer ...
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AD9887A The key to clamping is to identify a time when the graphics system is known to be producing a black signal. Originating from CRT displays, the electron beam is blanked by sending a black level during horizontal retrace to ...
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OFFSET GAIN 7 DAC DAC IN x1.2 CLAMP V OFF Figure 5. ADC Block Diagram (Single-Channel Output) OFFSET = 0x7F 1.0 0.5 0 0x00 GAIN Figure 6. Gain and Offset Control V 0.5V (128 CODES) V OFF (128 CODES) 0V ...
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AD9887A PIXEL CLOCK (MHz) Figure 10. Pixel Clock Jitter vs. Frequency Any jitter in the clock reduces the precision with which the sampling time can be determined and, thus, must be subtracted from ...
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Table 7. Recommended VCO Range and Charge-Pump Current Settings for Standard Display Formats Standard Resolution VGA 640 × 480 SVGA 800 × 600 XGA 1024 × 768 SXGA 1280 × 1024 UXGA 1600 × 1200 TV 480i 480p 720p 1080i ...
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AD9887A ALTERNATE PIXEL SAMPLING MODE Logic 1 input on CKINV (Pin 94) inverts the nominal ADC clock. CKINV can be switched between frames to implement the alternate pixel sampling mode. This allows higher effective image resolution to be achieved at ...
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TIMING—ANALOG INTERFACE The timing diagrams (Figure 18 through Figure 27) show the operation of the AD9887A analog interface in all clock modes. The part establishes timing by sending the pixel corresponding with the leading edge of Hsync to Data Port ...
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AD9887A RGB HSYNC PXCK HS ADCCK DATACK D OUTA HSOUT Figure 19. Single-Channel Mode, Alternate Pixel Sampling (Even Pixels, Analog Interface) RGB ...
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RGB HSYNC PXCK HS 8-PIPE DELAY ADCCK DATACK D OUTA D OUTB HSOUT Figure 22. Dual-Channel Mode, Parallel Outputs (Analog Interface), Outphase = RGB IN ...
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AD9887A RGB IN HSYNC PXCK HS ADCCK DATACK D OUTA D OUTB HSOUT Figure 25. Dual-Channel Mode, Parallel Outputs, Alternate Pixel Sampling (Even Pixels, Analog Interface), Outphase = 0 RGB P0 P1 ...
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THEORY OF OPERATION—INTERFACE DETECTION ACTIVE INTERFACE DETECTION AND SELECTION For interface detection in the AD9887A, the system should determine the correct interface and set the chip appropriately through the serial bus. An external circuit should be used to determine if ...
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AD9887A SCAN FUNCTION The scan function is intended as a pseudo JTAG function for the manufacturing test of the board. The ordinary operation of the AD9887A is disabled during scanning. To enable the scan function, set Register 0x14, Bit 2, ...
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THEORY OF OPERATION—DIGITAL INTERFACE CAPTURING ENCODED DATA The first step in recovering encoded data is to capture the raw data. To accomplish this, the AD9887A uses a high speed, phase-locked loop (PLL) to generate clocks capable of oversampling the data ...
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AD9887A DVI CONNECTOR DDC CLOCK DDC DATA DVI-VCC 3.3V 3.3V PULL-UP 5kΩ 5kΩ RESISTORS 150Ω DDCSCL SERIES AD9887A RESISTOR DDCSDA D S 3.3V RESISTOR Figure 32. HDCP Implementation Using the AD9887A Rev Page ...
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GENERAL TIMING DIAGRAMS—DIGITAL INTERFACE 80% 20% D LHT Figure 33. Digital Output Rise and Fall Times CIP CIP CIH CIH T CIL Figure 34. Clock Cycle/High/Low Times Rx0 DIFF Rx1 t ...
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AD9887A 2-WIRE SERIAL REGISTER MAP The AD9887A is initialized and controlled by a set of registers that determine the operating modes. An external controller is used to write and read the control registers through the 2-line serial interface port. Table ...
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Read and Write, or Default Address Read Only Bits Value ***1**** ****0*** *****0** ******0* *******0 0x10 R/W 7:2 0******* *0****** **11**** ****0*** *****1** 0x11 RO 7:1 1******* *1****** **1***** ***1**** ****1*** *****1** ******1* 0x12 R/W 7:0 0******* *0****** **0***** ***0**** ...
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AD9887A Read and Write, or Default Address Read Only Bits Value *****0** ******0* *******1 0x13 R/W 7:0 00100000 0x14 R/W 7:0 ***1**** ****0*** *****0** ******0* *******0 0x15 RO 7:5 0******* *0****** **0***** 0x16 R/W 7:2 10111*** *****1** 0x17 R/W 7:0 ...
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Read and Write, or Default Address Read Only Bits Value 0x22 R/W 7:0 00000000 0x23 R/W 7:0 00000000 0x24 R/W 7:0 00000000 0x25 R/W 7:0 11110000 0x26 R/W 7:0 11111111 0x27 00001111 1 The AD9887A only updates the PLL divide ...
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AD9887A 0x03 4–2 CURRENT Charge-Pump Current Three bits that establish the current driving the loop filter in the clock generator. Table 11. Charge-Pump Currents CURRENT Current (μA) 000 50 001 100 010 150 011 250 100 350 101 500 110 ...
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Green Channel Offset Adjust (GREENOFST) A 7-bit offset binary word that sets the dc offset of the green channel. See REDOFST (0B). 0x0D 7:1 Blue Channel Offset Adjust (BLUEOFST) A 7-bit offset binary word that sets the dc ...
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AD9887A 0x0F 7 HSYNC Input Polarity A bit that must be set to indicate the polarity of the Hsync signal that is applied to the PLL HSYNC input. Table 17. HSYNC Input Polarity (HSPOL) Settings HSPOL Function 0 Active low ...
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Green Clamp Select A bit that determines whether the green channel is clamped to ground or to midscale. Table 23. Green Clamp Select Settings Clamp Function 0 Clamp to ground 1 Clamp to midscale (Pin 109) The default ...
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AD9887A SYNC Detection/Active Interface Control 0x11 7 Analog Interface HSYNC Detect This bit is used to indicate when activity is detected on the HSYNC input pin (Pin 82). If HSYNC is held high or low, activity is not detected. Table ...
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Active VSYNC (AVS) This bit determines which VSYNC to use for the analog interface, the VSYNC input or the sync separator output. If both VSYNC and composite SOG are detected, VSYNC is selected. The user can override this ...
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AD9887A 0x12 0 PWRDN This bit can be used to fully power down both interfaces of the chip. See the Power Management section for details on which blocks are actually powered down. Note that the chip is unable to detect ...
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Precoast This register allows the coast signal to be applied prior to the Vsync signal. This is necessary in cases where pre- equalization pulses are present. This register defines the number of edges that are filtered before Vsync ...
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AD9887A 0x20 4 MDA/MCL Three-State This bit allows the MDA/MCL lines to be three-stated so that the HDCP key EEPROM can be programmed in-circuit. Table 57. MDA/MCL Three-State Select MDA/MCL Output 1 Normal operation 0 MDA/MCL set to three-state The ...
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Serial Control Port A 2-wire serial interface control port is provided four AD9887A devices can be connected to the 2-wire serial interface, with each device having a unique address. The 2-wire serial interface comprises a clock (SCL) ...
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AD9887A SDA t BUFF t DHO t STAH SCL SDA SCL t t DSU STASU t DAL t DAH Figure 41. Serial Port R/ W Timing BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 ...
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Serial Interface Read/Write Examples Write to one of the following control registers: • Start signal • Slave address byte (R/ W bit = low) • Base address byte • Data byte to base address • Stop signal Write to four ...
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AD9887A THEORY OF OPERATION—SYNC PROCESSING SYNC STRIPPER The purpose of the sync stripper is to extract the sync signal from the green graphics channel. A sync signal is not present on all graphics systems, only those with sync-on-green. The sync ...
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PCB LAYOUT RECOMMENDATIONS The AD9887A is a high performance, high speed analog device. To optimize its performance important to have a well laid out board. The following is a guide for designing a board using the AD9887A. ANALOG ...
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AD9887A PLL Place the PLL loop filter components as close as possible to the FILT pin. Do not place any digital or other high frequency traces near these components. Use the values suggested in the Specifications section with 10% tolerances ...
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... VIEW A ROTATED 90° CCW ORDERING GUIDE Model Max Speed (MHz) Analog AD9887AKS-100 100 1 AD9887AKSZ-100 100 AD9887AKS-140 140 1 AD9887AKSZ-140 140 AD9887AKS-170 170 AD9887AKSZ-170 1 170 AD9887A/PCB RoHS Compliant Part. 31.45 4.10 31.20 SQ 1.03 MAX 30.95 0.88 0.73 120 ...
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AD9887A NOTES ©2003–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02838-0-3/07(B) T Rev Page ...