AD9961BCPZRL Analog Devices Inc, AD9961BCPZRL Datasheet
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AD9961BCPZRL
Specifications of AD9961BCPZRL
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AD9961BCPZRL Summary of contents
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FEATURES Dual 10-bit/12-bit, 100 MSPS ADC SNR = 67 dB 30.1 MHz IN Dual 10-bit/12-bit, 170 MSPS DAC ACLR = 74 dBc 5 channels of analog auxiliary input/output Low power, <425 mW at maximum sample rates Supports full ...
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AD9961/AD9963 TABLE OF CONTENTS Features .............................................................................................. 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Specifications ..................................................................................... 3 Absolute Maximum Ratings ............................................................ 8 Thermal Resistance ...................................................................... 8 ESD Caution .................................................................................. 8 Pin Configurations and Function ...
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SPECIFICATIONS RX33V = TXVDD = CLK33V = DRVDD = AUX33V = 3.3 V. All LDOs enabled, I MIN MAX interpolation, unless otherwise noted. Table 1. Tx Path Specifications Parameter TxDAC DC CHARACTERISTICS Resolution Differential Nonlinearity Gain ...
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AD9961/AD9963 RX33V = TXVDD = CLK33V = DRVDD = AUX33V = 3.3 V. All LDOs enabled, ADC sample rate = 100 MSPS. No MIN MAX decimation, unless otherwise noted. Table 2. Rx Path Specifications Parameter Rx ...
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RX33V = TXVDD = CLK33V = DRVDD = AUX33V = 3.3 V. All LDOs enabled, unless otherwise noted. MIN MAX Table 3. Auxiliary Converter Specifications Parameter AUXILIARY DAC12A/AUXDAC12B Resolution Differential Nonlinearity Gain Error Settling Time (±1%) ...
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AD9961/AD9963 f = 125 MHz 250 MHz, DAC sample rate = 125 MSPS, ADC sample rate = 62.5 MSPS, unless otherwise noted. CLK DLL Table 4. Power Consumption Specifications Parameter 1.8 V ONLY OPERATION (EXTERNAL 1.8 V) CLK33V ...
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Table 5. Digital Logic Level Specifications Parameter CMOS INPUT LOGIC LEVEL V Logic High IN V Logic High IN V Logic High IN V Logic Low IN V Logic Low IN V Logic Low IN CMOS OUTPUT LOGIC LEVEL V ...
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AD9961/AD9963 ABSOLUTE MAXIMUM RATINGS Table 6. With Parameter Respect to RX33V, AUX33V RXGND TXVDD TXGND DRVDD DGND CLK33V EPAD RX18V, RX18VF RXGND DVDD18V EPAD CLK18V, DLL18V EPAD RXGND, TXGND, DGND, EPAD TXIP, TXIN, TXQP, TXQN TXGND RXIP, RXIN, RXQP, RXQN ...
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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS AUX33V AUXADCREF RXGND RXBIAS RX18VF RXGND LDO_EN NOTES 1. EXPOSED PAD MUST BE SOLDERED TO PCB CONNECT. Table 8. AD9961 Pin Function Descriptions Pin No. Mnemonic Description 1 AUX33V Analog Supply ...
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AD9961/AD9963 Pin No. Mnemonic Description 36 TRXCLK Qualifying Clock for the TRXD Bus. 37 TXCLK Qualifying Clock for the TXD Bus. It can be configured as either an input or output. 38 TXIQ/TXnRX Dual Function Pin. In half-duplex mode (TXnRX), ...
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AUX33V AUXADCREF RXGND RXBIAS RX18VF RXGND LDO_EN NOTES 1. EXPOSED PAD MUST BE SOLDERED TO PCB. Table 9. AD9963 Pin Function Descriptions Pin No. Mnemonic Description 1 AUX33V Analog Supply for the Auxiliary ADC and Auxiliary DACs (3.3 V ± ...
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AD9961/AD9963 Pin No. Mnemonic Description 54 DLLFILT DLL Filter Output. 55 CLK18V Output of CLK18V Voltage Regulator. 56,57 CLKN, CLKP Differential Input Clock. 58 CLK33V Input to CLK18V and DLL18V Voltage Regulators (1 3.3 V). If LDOs are ...
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TYPICAL PERFORMANCE CHARACTERISTICS 2mA 1mA (MHz) OUT Figure 4. Second Harmonic Distortion vs. f OUT f = 125 MHz, 1×, Digital ...
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AD9961/AD9963 100 0dBFS 75 –3dBFS 70 65 –6dBFS (MHz) OUT Figure 10. Second Harmonic Distortion vs 125 MHz, 1×, Full-Scale Current = 2 mA, TXVDD = 3.3 ...
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TEMPER ATURE (°C) Figure 16. Typical Die Temperature Readback Error vs. Ambient Temperature REF ...
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AD9961/AD9963 1.2 1.0 0.8 INL 0.6 DNL 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 –1.2 0 512 1024 1536 2048 2560 CODE Figure 22. Rx Path ADC, INL and DNL 155 IDAC, 125MHz, 4mA, 0dB 153 151 IDAC, 125MHz, ...
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MIN PIPE SFDR (dBFS) MID PIPE SFDR (dBFS) MAX PIPE SFDR (dBFS) 80 MIN PIPE SNR (dBFS) MID PIPE SNR (dBFS) 75 MAX PIPE SNR (dBFS ...
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AD9961/AD9963 TERMINOLOGY Linearity Error (Integral Nonlinearity or INL) Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. Differential Nonlinearity (DNL) ...
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THEORY OF OPERATION The AD9961/AD9963 are targeted to cover the mixed-signal front-end needs of multiple wireless communications systems. They feature a receive path that consists of dual 10-/12-bit receive ADCs and a transmit path that consists of dual 10-/12-bit transmit ...
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AD9961/AD9963 SERIAL CONTROL PORT The AD9961/AD9963 serial control ports are a flexible, synchronous, serial communications port that allows an easy interface with many industry-standard microcontrollers and microprocessors. The AD9961/AD9963 serial control ports are compatible with most synchronous transfer formats, including ...
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When LSB first is set by Register 0x00, Bit 2 and Register 0x00, Bit 6, it takes effect immediately. In multibyte transfers, subsequent bytes reflect any changes in the serial port configuration. To avoid problems reconfiguring the serial port operation, ...
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AD9961/AD9963 SCLK SDIO CS SCLK DON’T CARE SDIO DON’T CARE 16-BIT INSTRUCTION HEADER Figure 37. Serial Control Port Access—LSB First, 16-Bit Instruction, Two Bytes Data SCLK SDIO Table ...
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CONFIGURATION REGISTERS Table 14. Configuration Register Map Addr Default Bit 7 Bit 6 0x00 0x18 SDIO LSB First 0x05 0x00 0x0F 0x00 0x10 0x00 Unused 0x30 0x3F Unused 0x31 0xA7 TX_SDR TXCKO_INV 0x32 0xA7 RX_SDR Unused 0x33 Varies Unused FIFO_INIT ...
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AD9961/AD9963 Addr Default Bit 7 Bit 6 0x71 0x00 ADCCLKSEL DACCLKSEL 0x72 0x01 DLL_Locked 0x75 0x00 0x77 0x00 CONV_TIME[1:0] 0x78 Varies 0x79 Varies 0x7A 0x00 AUXADC_EN AUXADC_RESB 0x7B 0x00 TMPSNS_EN 0x7D 0x00 Unused 0x7E 0x00 Unused RXTrim_EN 0x7F 0x00 0x80 ...
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Register Register Name Address Bit( Data Interface 0x31 Data Interface 0x32 7 6 5:4 Parameter Function SRRC_BP 1: bypass 2× SRRC interpolation filter (SRRC). The filter chain is ...
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AD9961/AD9963 Register Register Name Address Bit( FIFO Alignment 0x33 2:0 FIFO Status 0x34 7:0 Tx Scale P 0x35 7:5 4:0 Tx Scale 0 0x36 7:5 4:0 Parameter Function 11: RXCLK is ...
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Register Register Name Address Bit(s) Tx Scale 1 0x37 7:5 4:0 Rx Scale 0x38 7:5 4:0 Clock Doubler 0x39 7 Config 6 5 Clock Doubler 0x3A 7:4 Config Clock Doubler 0x3B ...
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AD9961/AD9963 Register Register Name Address Bit(s) Rx Data Interface 0x3F DAC12 Config 0x40 3 DAC12A MSBs 0x41 7:0 DAC12A LSBs 0x42 7:4 3:0 DAC12B MSBs 0x43 ...
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Register Register Name Address Bit(s) 1:0 DAC10BMSBs 0x46 7:0 DAC10BLSBs 0x47 7:2 1:0 DAC10A Config 0x48 7 6:5 4:2 1:0 DAC10A MSBs 0x49 7:0 DAC10A LSBs 0x4A 7:2 1:0 TX BIST Control 0x50 7 ...
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AD9961/AD9963 Register Register Name Address Bit( TXI Check MSB 0x52 7:0 TXI Check LSB 0x53 7:0 TXQ Check MSB 0x54 7:0 TXQ Check LSB 0x55 7:0 Version 0x5C 7:0 Power Down 0 0x60 ...
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Register Register Name Address Bit(s) 3:2 1:0 Clock Mode 0x66 1:0 I DAC Gain Ctrl 0 0x68 7:6 5:0 I DAC Gain Ctrl 1 0x69 7:6 5:0 I DAC Gain Ctrl 2 0x6A 7:6 ...
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AD9961/AD9963 Register Register Name Address Bit(s) DLL Control 0 0x71 3:0 DLL Control 1 0x72 7 6:5 4:0 DLL Control 2 0x75 7:4 3 2:0 Aux ADC Config 0x77 7:6 and Conversion Start 5:3 2:0 Parameter ...
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Register Register Name Address Bit(s) Aux ADC MSBs 0x78 7:0 Aux ADC LSBs 0x79 7:4 3 2:0 Aux ADC CTRL 0 0x7A 7 6 5:3 2:0 Aux ADC CTRL 1 0x7B 7 6:5 4:2 1:0 ADC Full-Scale Adj 0x7D 7:5 ...
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AD9961/AD9963 Register Register Name Address Bit(s) Rx ADC Trim Ctrl 0x7E 3:1 0 IGAIN CAL MSBs 0x7F 7:0 IGAIN CAL LSBS 0x80 7:3 2:1 0 IGAIN CAL MSBs 0x81 7:0 IGAIN CAL LSBs 0x82 7:3 2:1 ...
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RECEIVE PATH Rx Path General Description The AD9961/AD9963 Rx paths consist of dual, differential input, 100 MSPS ADCs followed by an optional 2× decimation filter. The Rx path also has digital offset and gain adjustments. I OFFSET RXIP I ADC ...
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AD9961/AD9963 200Ω 200Ω +VIN V ADA4937 CC 33Ω 1kΩ VOCM 0.1µF 1kΩ 33Ω –VIN 200Ω 200Ω Figure 41. Differential Input Configuration, AC-Coupled The output common-mode voltage of the match the common-mode voltage required by the ADC by connecting the RXCML ...
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NORMALIZED FREQUENCY (Relative to f Figure 46. Pass-Band Response of the Rx Path Decimation Filter The filter coefficients of the 2× decimation low-pass are shown in Table 16. Table 16. Lower ...
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AD9961/AD9963 TRANSMIT PATH Tx Path General Description The transmit section consists of two complete paths of interpolation filters stages, each followed by a high speed current output DAC. A data assembler receives interleaved data from one of two digital interface ...
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Interpolation Filter Coefficients The interpolation filters, INT0 and INT1, are half-band filters implemented with a symmetric set of coefficients. Every other coefficient (even coefficients) except the center coefficient is zero. The coefficient values for the three interpolation filters are listed ...
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AD9961/AD9963 13 TXD[11:0] INPUT TXIQ LATCH TXCLK_MD 1 0 Reg 0x31[0] TXCKI_INV 1 0 Reg 0x31[3] EN TXCLK TXCKO_INV Reg 0x31[6] Figure 52. Transmit Path Data Flow and Clock Generation In Full Duplex Mode The signal on ...
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Transmit Path Gain Adjustment Adjusting the output signal level is implemented by scaling the full-scale output current of the transmit DAC. There are four separate programmable parameters that can be used to adjust the full-scale output of the DACs; the ...
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AD9961/AD9963 –2 –4 –6 – GAIN1 Figure 56. Typical DAC Full-Scale Current vs. GAIN1 Code 2.06 2.04 2.02 2.00 1.98 1.96 1. GAIN2 Figure ...
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The circuit shown in Figure 60 shows a typical output circuit configuration that provides a non zero bias voltage at the TXCML pin. Resistance values of 499 Ω for R R produces p-p differential output voltage swing ...
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AD9961/AD9963 R B AD9961/AD9963 R S TXIP 65 REFIO 63 C TXGND TXIN Figure 62. Single-Supply Differential Buffer Single-Ended Buffered Output Using an Op Amp An op amp such as the ADA4899-1 can be ...
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DEVICE CLOCKING CLOCK DISTRIBUTION The clock distribution diagram shown in Figure 65 gives an overview of the clocking options for each of the data converters. The receive path ADCs and the transmit path DACs can be clocked directly from the ...
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AD9961/AD9963 DRIVING THE CLOCK INPUT For optimum performance, the AD9961/AD9963 clock inputs (CLKP and CLKN) should be clocked with a low jitter, fast rise time differential signal. This signal should be ac-coupled to the CLKP and CLKN pins via a ...
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The DLL is composed of a ring oscillator made from a programmable delay line. The ring oscillator output signal is labeled as MCLK. The MCLK signal is set to oscillate at a frequency M times greater than the REFCLK signal. ...
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AD9961/AD9963 DIGITAL INTERFACES The AD9961/AD9963 have two parallel interface ports, the Tx port and the TRx port. The operation of the ports depends on whether the device is configured for full-duplex or half- duplex mode. In full-duplex mode, the TRx ...
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TRXCLK TRXIQ TRXD[11:0] I0 Figure 75. Rx Timing, I ADC Only, Bus Rate Clock Mode t OD2 TRXCLK TRXIQ TRXD[11:0] Q0 Figure 76. Rx Timing, Q ADC Only, Bus Rate Clock Mode t OD2 TRXCLK TRXIQ TRXD[11:0] I0 Figure ...
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AD9961/AD9963 The Tx port has an optional double data rate (DDR) clock mode. In DDR mode, the transmit data is latched on both the rising and falling edges of TXCLK. The polarity of the edge identifies to which channel the ...
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Table 26 shows the operating modes vs. serial port configuration bits. Table 26. TRx Bus Operation via Serial Port TRXD Bus TXEN RXEN Direction 0 0 High Table 27 shows the ...
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AD9961/AD9963 AUXILIARY CONVERTERS The AD9961/AD9963 have two fast settling servo DACs, along with an analog input and two analog I/O pins. All of the auxiliary converters run off a dedicated supply pin. The input and output compliance ranges depend on ...
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Digital Output Coding The digital output coding is straight binary. The ideal transfer characteristic for the auxiliary ADC is shown in Figure 86. 111 ... 111 111 ... 110 111 ... 101 000 ... 010 000 ... 001 000 ... ...
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AD9961/AD9963 The curves in Figure 89 represent four of the possible DAC transfer functions with the full-scale voltage of 3.0 V and spans of 0.5 V, 1.0 V, 1.5 V, and 2.0 V. The curves in Figure 90 represent four ...
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POWER SUPPLIES The AD9961/AD9963 power distributions are shown in Figure 93. The functional blocks labeled Rx ANLG, Rx ADCs, SPI and digital core, clocking, and DLL operate from 1.8 V supplies. The functional blocks labeled Tx DACs, AUX DACs and ...
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AD9961/AD9963 80 RX18V RX18VF (MHz) ADC Figure 96. I and I vs Both ADCs Enabled RX18V RX18VF ADC 4mA ...
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DAC Figure 102 1×, 2×, 4×, 8× (Tx only) DVDD18 DAC 3.3V 2.5V 15 1.8V ...
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... SEATING PLANE ORDERING GUIDE 1 Model Temperature Range AD9961BCPZ −40°C to +85°C AD9961BCPZRL −40°C to +85°C AD9963BCPZ −40°C to +85°C AD9963BCPZRL −40°C to +85°C AD9961-EBZ −40°C to +85°C AD9963-EBZ −40°C to +85°C HSC-DAC-EVALCZ − ...
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NOTES Rev Page AD9961/AD9963 ...
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AD9961/AD9963 NOTES ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08801-0-7/10(0) Rev Page ...