AD9961BCPZRL Analog Devices Inc, AD9961BCPZRL Datasheet - Page 30
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AD9961BCPZRL
Manufacturer Part Number
AD9961BCPZRL
Description
Dual 16B, 200 MSPS D-A Converter
Manufacturer
Analog Devices Inc
Datasheet
1.AD9961BCPZRL.pdf
(60 pages)
Specifications of AD9961BCPZRL
Features
*
Package / Case
72-VFQFN, CSP Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
AD9961/AD9963
Register Name
TXI Check MSB
TXI Check LSB
TXQ Check MSB
TXQ Check LSB
Version
Power Down 0
Power Down 1
LDO Status
Output Drive
Register
Address
0x52
0x53
0x54
0x55
0x5C
0x60
0x61
0x62
0x63
Bit(s)
1
0
7:0
7:0
7:0
7:0
7:0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7:6
5:4
Parameter
RX_START
RX_BISTEN
TXI_CHK[15:8]
TXI_CHK[7:0]
TXQ_CHK[15:8]
TXQ_CHK[7:0]
Chip ID[7:0]
DLL_EN
TXDAC_PD
TXI_SLEEP
TXQ_SLEEP
CLK_PD
RXADC_PD
RXQ_SLEEP
RXI_SLEEP
Unused
DLL_LDO_PD
DLLBIAS_PD
CLK_LDO_PD
RX_LDO_PD
RXF_LDO_PD
AUXADC_PD
AUX_REF_PD
DLL_LDO_STAT
CLK_LDO_STAT
RX_LDO_STAT
RXF_LDO_STAT
DIG_LDO_STAT
Unused
Unused
RSET_SEL
TRXD_DRV
TRXIQ_DRV
Rev. 0 | Page 30 of 60
Function
0: keep the BIST engine in an idle state.
1: start the BIST sequence.
0: disable the BIST engine.
1: enable the BIST engine.
MSB of the BIST signature value for the I side transmit path.
LSB of the BIST signature value for the I side transmit path.
MSB of the BIST signature value for the Q side transmit path.
LSB of the BIST signature value for the Q side transmit path.
Indicates device hardware revision number. Should read back as 0x08.
0: powers down DLL block.
1: enables DLL block.
1: powers down the bandgap reference voltage common to both
transmit DACs and all of the auxiliary DACs.
1: turns off IDAC output current.
1: turns off QDAC output current.
1: turns off clock receiver. This disables all clocks on the chip except for
the serial port clock.
1: powers down main ADC clock and the bandgap reference voltage
common to both receive ADCs.
1: powers down the Q ADC core.
1: powers down the I ADC core.
1: powers down LDO that supplies the DLL18V voltage rail.
1: powers down bias sub-block inside DLL block.
1: powers down LDO that supplies the CLK18V voltage rail.
1: powers down LDO that supplies the RX18V voltage rail.
1: powers down LDO that supplies the RX18VF voltage rail.
1: powers down AUXADC block.
1: powers down the auxiliary ADC voltage reference, allowing an external
reference to be used.
1: LDO to DLL block is on (read only).
1: LDO to CLOCK block is on (read only).
1: LDO to ADC blocks is on (read only).
1: LDO to FLASH section of ADC is on (read only).
1: LDO to digital core is on (read only).
0: selects internal 10 kΩ to generate 1 V reference.
1: selects external RSET to generate voltage reference.
Controls the drive strength of the TRXD[11:0] pins.
00: 4 mA output drive.
01: 8 mA output drive.
10: 12 mA output drive.
11: not valid.
Controls the drive strength of the TRXIQ pin.
00: 4 mA output drive.
01: 8 mA output drive.
10: 12 mA output drive.
11: not valid.