ADATE302-02BSVZ Analog Devices Inc, ADATE302-02BSVZ Datasheet
ADATE302-02BSVZ
Specifications of ADATE302-02BSVZ
Available stocks
Related parts for ADATE302-02BSVZ
ADATE302-02BSVZ Summary of contents
Page 1
... The output voltage range is −2 +6 accommodate a wide variety of test devices. The ADATE302-02 can be used as either a dual single-ended drive/receive channel or a single differential drive/receive channel. Each channel of the ADATE302-02 features a high speed window comparator for functional testing as well as a per pin PMU with and functions ...
Page 2
... ADATE302-02 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Functional Block Diagram .............................................................. 3 Specifications ..................................................................................... 4 Total Function ............................................................................... 4 Driver ............................................................................................. 5 Reflection Clamp .......................................................................... 7 Normal Window Comparator .................................................... 7 Differential Comparator .............................................................. 9 Active Load .................................................................................. 11 PMU ............................................................................................. 12 External Sense (PMUS_CHx) ................................................... 16 DUTGND Input ......................................................................... 17 Serial Peripheral Interface ......................................................... 17 HVOUT Driver ........................................................................... 17 Overvoltage Detector (OVD) ................................................... 18 16-Bit DAC Monitor Mux ......................................................... 19 REVISION HISTORY 4/09— ...
Page 3
... ONE PER DEVICE. PMU_FLAG PMU MUX CH1 VCH VCL (TRIMMED) DRV WINDOW DIFF VHH * G IOL VCOM IOH Figure 1. Functional Block Diagram with One of Two Channels Shown Rev Page ADATE302-02 OVD OUT * OTHER CHANNEL DUT1 C VOH C VOL ADATE302-02 * TEMPERATURE SENSOR OVD_CH0 DUT0 HVOUT TEMPSENSE ...
Page 4
... ADATE302-02 SPECIFICATIONS −5. defined in Table 38. All specified values are at T Temperature coefficients are measured at T analyses, and/or limited bench evaluations. Typical values are not tested or guaranteed. Test levels are specified in the Explanation of Test Levels section. TOTAL FUNCTION Table 1. Parameter TOTAL FUNCTION ...
Page 5
... 0.0 V, terminated; 20% to 80% B 589 3 0.0 V, terminated; 20% to 80% B 811 3 0.0 V, unterminated; 10% to 90% B 1105 5 0.0 V, unterminated; 10 0.0 V, terminated; rise to fall within one channel B Rev Page ADATE302- and 50 mA; DUTx = −1 mA and −50 mA; ΔV /ΔI DUTx DUTx DUTx ...
Page 6
... ADATE302-02 Parameter Min Minimum Pulse Width 2.0 V Programmed Swing Maximum Toggle Rate Dynamic Performance, Drive ( and VL to VH) Propagation Delay Time Propagation Delay Tempco Delay Matching Edge to Edge Channel to Channel Delay Change vs. Duty Cycle Overshoot and Undershoot Settling Time (VH to VL) To Within 3% of Final Value ...
Page 7
... Rev Page ADATE302-02 Conditions/Comments Driver high-Z, sinking 1 mA; VCH error measured at calibration points and 5 V Driver high-Z, sinking 1 mA; after two-point gain/offset calibration; range/number of DAC bits as measured at calibration points and 5 V Driver high-Z, sinking 1 mA; after two-point gain/offset calibration Driver high-Z, sinking 1 mA ...
Page 8
... ADATE302-02 Parameter DUTGND Voltage Accuracy Comparator Uncertainty Range DC Hysteresis DC PSRR Digital Output Characteristics Internal Pull-Up Resistance to Comparator, COMP_VTTx Pin V Range COMP_VTTx Common-Mode Voltage Differential Voltage Rise/Fall Time, 20% to 80% AC SPECIFICATIONS Propagation Delay, Input to Output Propagation Delay Tempco Propagation Delay Matching High Transition to Low Transition ...
Page 9
... T 1 ps/° ± Rev Page ADATE302-02 Test Level Conditions/Comments 1.0 V swing, driver VTERM mode, B DUTx VT = 0.0 V; less than 10% amplitude degradation measured by shmoo; input transition time = 400 ps (10%/90 1.0 V swing, driver VTERM mode, B DUTx measured by shmoo; input transition time = 400 ps (10%/90%) ...
Page 10
... ADATE302-02 Parameter Slew Rate, 400 ps and 1 ns (10% to 90%) Overdrive, 250 mV and 750 mV Pulse Width, 1 ns, 5 ns, 10 ns, and 15 ns Duty Cycle 95% Minimum Pulse Width Input Equivalent Bandwidth, Terminated Test Min Typ Max Unit Level 500 MHz C B Rev Page Conditions/Comments VOL = 0.0 V; repeat for other DUT channel ...
Page 11
... V P ±1.5 μA/° Rev Page ADATE302-02 Conditions/Comments Load active on, RCVx pins active, unless otherwise noted IOH = IOL = 6 mA, VCOM error measured at calibration points and 5 V IOH = IOL = 6 mA, after two-point gain/offset calibration; range/number of DAC bits as measured at calibration points and 5 V IOH = IOL = 6 mA, after two-point gain/offset calibration IOH = IOL = 6 mA, after two-point gain/offset calibration ...
Page 12
... ADATE302-02 Parameter Min AC SPECIFICATIONS Dynamic Performance Propagation Delay, Load Active On to Load Active Off; 50%, 90% Propagation Delay, Load Active Off to Load Active On; 50%, 90% Propagation Delay Matching Load Spike Settling Time to 90% PMU FV = force voltage measure voltage force current measure current force nothing. ...
Page 13
... PMU enabled, FVMI, PE disabled, force −1 V and +5 V into load of 1 mA; measure ΔI reported at MEASOUT01 ±2 Over ±0.1 V range; measured at end points of MI functional T range Rev Page ADATE302-02 externally forced to 0.0 V, unless otherwise specified; [ × 5/FSR MEASOUT01 DUTGND ) [ − V − 2.5) × FSR/5 ...
Page 14
... ADATE302-02 Parameter Min FORCE CURRENT (FI) Force Current, DUTx Pin Voltage −2.0 Range for All Ranges Force Current Uncalibrated Accuracy Range A −5.0 Range B −400 Range C −40 Range D −4 Range E −400 Force Current Offset Tempco Range A Range B Range C to Range E Forced Current Gain Error, − ...
Page 15
... V; simulation of worst case, 2000 pF load, PMUDAC step of 5 μ μs S 124 μs S 1015 μs S 3455 μs S PMU enabled, FV, PE disabled, start with PMUDAC programmed to 0.0 V, program PMUDAC to 500 mV 8.0 μ 8.0 μ 8.0 μ 8.1 μ 585 μ 8.1 μ 590 μ Rev Page ADATE302-02 ...
Page 16
... ADATE302-02 Parameter Min Voltage Force Settling Time to 1.0% of Final Value Range A, 200 pF and 2000 pF Load Range B, 200 pF Load Range B, 2000 pF Load Range C, 200 pF Load Range C, 2000 pF Load Range D, 200 pF Load Range D, 2000 pF Load Range E, 200 pF Load Range E, 2000 pF Load Current Force Settling Time to ...
Page 17
... P ± Ω P 100 mA P − 175 Rev Page ADATE302-02 Test Level Conditions/Comments D P Tested at −100 mV and +100 mV Conditions/Comments F F Tested at 0.0 V and 3 disabled, PMU FV enabled and forcing Sourcing Sinking Maximum delay time required for the part to enter a stable state after a serial bus command is loaded Conditions/Comments VHH = ( × ...
Page 18
... ADATE302-02 Parameter Min Fall Time (From VHH VH) Preshoot, Overshoot, and Undershoot VL/VH BUFFER Voltage Range −0.1 Accuracy Uncalibrated −500 Offset Tempco Resolution INL −20 DUTGND Voltage Accuracy Output Resistance 46 DC Output Current Limit Source 60 DC Output Current Limit Sink −100 Rise Time (VL to VH) ...
Page 19
... DAC MONITOR MUX Table 13. Parameter Min DC CHARACTERISTICS Programmable Voltage Range −2.5 Output Resistance Test Typ Max Unit Level +7 kΩ Rev Page ADATE302-02 Conditions/Comments PMUDAC = 0 μA, 200 μA; ΔV/ΔI ...
Page 20
... Ω − DCL current limit. Continuous short-circuit L DUTx condition. ADATE302-02 must current limit and survive continuous short circuit. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Rating rating only; functional operation of the device at these or any other conditions above those indicated in the operational − ...
Page 21
... Driver Output Supply +10.0 V Channel 1 Driver Output Supply +10.0 V Channel 0 Device Under Test Channel 0 Driver Output Supply −5.75 V Channel 0 PMU External Sense Path Channel 0 High Voltage Driver Output Temperature Sense Supply +10.0 V PMU Stability Capacitor Connection Channel 1 (330 pF) Rev Page ADATE302- VSSO_1 DUT1 PMUS_CH1 TEMPSENSE ...
Page 22
... ADATE302-02 BGA Designator Mnemonic B3 VSS B4 AGND B5 VDD B6 VDD B7 AGND B8 VSS B9 SCAP0 B10 VPLUS C1 FFCAP_1B C2 AGND C3 DATA1N C4 VSS C5 VDD C6 VDD C7 VSS C8 DATA0N C9 AGND C10 FFCAP_0B D1 OVD_CH1 D2 VDD D3 DATA1P D8 DATA0P D9 VDD D10 OVD_CH0 E1 FFCAP_1A E2 VSS E3 RCV1N E8 RCV0N E9 VSS E10 FFCAP_0A F1 AGND F2 AGND F3 RCV1P ...
Page 23
... Temperature Sense and Temperature Sense GND Reference DUT Ground Reference Analog Ground Serial Peripheral Interface (SPI) Chip Select Serial Peripheral Interface (SPI) Data Out Serial Peripheral Interface (SPI) Clock Supply +3.3 V Analog Ground +5 V DAC Reference Voltage DAC Ground Reference Rev Page ADATE302-02 ...
Page 24
... PIN 1 ADATE302-02 TOP VIEW (Not to Scale Figure 3. 100-Lead TQFP_EP Pin Configuration Description No Connect. No physical connection to die. No Connect. No physical connection to die. Temperature Sense Output. Temperature Sense Supply +10.0 V. PMU Stability Capacitor Connection Channel 1 (330 pF). PMU Feed Forward Capacitor Connection B Channel 1 (220 pF). ...
Page 25
... No Connect. No physical connection to die. No Connect. No physical connection to die. No Connect. No physical connection to die. Analog Ground. Analog Ground. Analog Ground. High-Side Comparator Output (Negative) Channel 0. High-Side Comparator Output (Positive) Channel 0. Comparator Supply Channel 0. Low-Side Comparator Output (Negative) Channel 0. Low-Side Comparator Output (Positive) Channel 0. Rev Page ADATE302-02 ...
Page 26
... ADATE302-02 Pin No. Mnemonic 61 AGND 62 RCV0P 63 RCV0N 64 VSS 65 FFCAP_0A 66 DATA0P 67 DATA0N 68 OVD_CH0 69 VDD 70 FFCAP_0B 71 SCAP0 72 VPLUS 73 HVOUT PMUS_CH0 79 VSS 80 VDD 81 VSSO_0 (DRIVE) 82 DUT0 83 VDDO_0 (DRIVE) 84 AGND 85 AGND 86 VSS 87 VDD 88 AGND 89 VDD 90 VSS 91 AGND 92 AGND 93 VDDO_1 (DRIVE) 94 DUT1 95 VSSO_1 (DRIVE) 96 VDD 97 VSS 98 PMUS_CH1 ...
Page 27
... Figure 8. 300 MHz Driver Response 1.0 V, 2 0.0 V; 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0 Figure 9. 400 MHz Driver Response 0.5 V, 1.0 V, 2 0.0 V; Rev Page ADATE302- TIME (ns) 50 Ω Termination TIME (ns) 50 Ω Termination ...
Page 28
... ADATE302-02 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0 0.5 1.0 1.5 2.0 2.5 3.0 TIME (ns) Figure 10. 500 MHz Driver Response 0.5 V, 1.0 V, 2 Ω Termination 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0 0.5 1.0 1.5 2.0 2.5 3.0 TIME (ns) Figure 11. 600 MHz Driver Response ...
Page 29
... Figure 20. Driver VH Linearity Error 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –2.5 10 –2 –1 0 Figure 21. Driver VL Linearity Error Rev Page ADATE302-02 NEGATIVE PULSE POSITIVE PULSE 10 PULSE WIDTH ( DRIVER OUTPUT VOLTAGE ( DRIVER OUTPUT VOLTAGE (V) ...
Page 30
... ADATE302-02 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –2.5 –3.0 –2 – DRIVER OUTPUT VOLTAGE (V) Figure 22. Driver VT Linearity Error 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 –0.2 –2 – PROGRAMMED VL DAC LEVEL (V) Figure 23. Driver Interaction Error 6 Swept from −2 +5.9 V ...
Page 31
... Rev Page ADATE302- VHH PROGRAMMED VOLTAGE (V) Figure 31. HVOUT VHH Linearity Error (V) HVOUT Figure 32. HVOUT VH Current Limit −0 Swept from −0 +6.0 V HVOUT (V) HVOUT Figure 33. HVOUT VHH Current Limit; VHH = 10 Swept from 5 ...
Page 32
... ADATE302-02 1.1 1.0 0.9 0.8 0.7 0.6 INPUT EDGE SHMOO 0.5 0.4 0.3 0.2 0.1 0 –0.1 0 1.2 2.4 3.6 TIME (ns) Figure 34. Comparator Shmoo; 1.0 V Swing; 200 ps (10%/90%) 1.1 1.0 INPUT EDGE 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 –0 ...
Page 33
... Figure 45. DUTx Pin Leakage Current in Low Leakage Mode Rev Page ADATE302- ACTIVE LOAD CURRENT (mA) Figure 43. Active Load Current Linearity – VCOM VOLTAGE (V) Figure 44. Active Load VCOM Linearity – ...
Page 34
... ADATE302- –2 –4 –6 –2 – (V) DUTx Figure 46. DUTx Pin Leakage Current in High-Z Mode 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.20 –0.15 –0.10 –0.05 0 0.05 DUTGND VOLTAGE (mV) Figure 47. DUTGND Voltage Effects 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 –1.2 – ...
Page 35
... Figure 56. PMU Force Voltage Range A Output Voltage Error at 6 –1 –2 –3 –4 1.0 1.5 2.0 –25 Figure 57. PMU Force Voltage Range A Output Voltage Error at −2.0 V vs. Rev Page ADATE302-02 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 I (mA) DUTx Output Current –20 –15 –10 –5 ...
Page 36
... ADATE302- –2 –4 –6 –8 –10 –2 – (V) DUTx Figure 58. PMU Force Current Range A Output Current Error at −25 mA vs. Output Voltage 10 0 –10 –20 –30 –40 –50 –60 –2 – (V) DUTx Figure 59. PMU Force Current Range A Output Current Error vs. Output Voltage; Output Voltage Is Pulled Externally 1 ...
Page 37
... V (V) DUTx Figure 66. PMU Range B Measure Voltage Linearity –0.05 –0. Figure 68. PMU Measure Current CMRR, Externally Pulling 1 mA, FVMI Rev Page ADATE302-02 0.20 0.15 0.10 0.05 0 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 I (mA) DUTx Figure 67. PMU Range B Measure Current Linearity 0.7 ...
Page 38
... ADATE302-02 500ps/DIV Figure 70. Eye Diagram, 400 Mbps, PRBS31 1 0.0 V 500ps/DIV Figure 71. Eye Diagram, 400 Mbps, PRBS31 2 0.0 V 200ps/DIV Figure 72. Eye Diagram, 800 Mbps, PRBS31 1 0.0 V Figure 73. Eye Diagram, 800 Mbps, PRBS31 2.0 V; VL= 0.0 V Figure 74. Eye Diagram, 1000 Mbps, PRBS31 1 0.0 V Figure 75. Eye Diagram, 1000 Mbps, PRBS31 ...
Page 39
... R/W DO_14 DO_13 DO_12 LAST LAST LAST t DO Figure 76. SPI Timing Diagram Min 9.0 9.0 3.0 3.0 3.0 3.0 3.0 3 this allows any internal Rev Page ADATE302-02 t CSSD t CSHD t CSW ADDR[1] ADDR[0] DO_2 DO_1 DO_0 LAST LAST LAST Max Unit 15.0 ...
Page 40
... ADATE302-02 DEFINITION OF SPI WORD The SPI can take variable length words, depending on the operation. At most, the word is 24 bits longs: 16 bits of data, two channel selects, one R/W selector, and a 5-bit address. Depending on the operation, the data can be smaller (or nonexistent in the case of a read operation). ...
Page 41
... DATA[15] DATA[14] DATA[13] INPUT SDOUT OUTPUT R INPUT SCLK INPUT SDIN DATA[1] DATA[0] CH[1] CH[0] INPUT SDOUT OUTPUT R CH[1] CH[0] R/W ADDR[ Figure 82. 16-Bit SPI Write R/W ADDR[4] ADDR[3] ADDR[2] ADDR[1] ADDR[ Figure 83. 2-Bit SPI Write Rev Page ADATE302-02 X ADDR[3] ADDR[2] ADDR[1] ADDR[ ...
Page 42
... ADATE302-02 READ OPERATION The read operation is a two-stage operation. First, a word is shifted in, specifying which register to read deasserted for three clock cycles, and then a second word is shifted in to get the readback data. This second word can be either another operation or an NOP address. If another operation is shifted in, ...
Page 43
... RESET OPERATION The ADATE302-02 contains an asynchronous reset feature. The ADATE302-02 can be reset to the default values shown in Table 21 RST CS SCLK MINIMUM OF TWO SCLK EDGES AFTER ASSERTING RST BEFORE RESUMING NORMAL OPERATION. by utilizing the RST pin. To initiate the reset operation, deassert the RST pin for a minimum of 100 ns and deassert the CS pin for a minimum of two SCLK cycles ...
Page 44
... ADATE302-02 REGISTER MAP The ADDR[4:0] bits determine the destination register of the data being written to the ADATE302-02. Table 21. Register Selection Data[15:0] CH[1:0] N/A N/A Data[13:0] CH[1:0] Data[13:0] CH[1:0] Data[13:0] CH[1:0] Data[13:0] CH[1:0] Data[13:0] CH[1:0] Data[13:0] CH[1:0] Data[13:0] CH[1:0] Data[13:0] CH[1:0] Data[13:0] CH[1:0] ...
Page 45
... Note that when the ADDR[4:0] = 0x0C PMU enable bit (Data[2 the PMU force outputs and clamps are disabled, and the PMU is placed into measure voltage mode. Data[9:8] and Data[6:0] of the PMU state register are ignored, and only Data[7], the PMU sense path bit, is valid don’t care (calibrated for 0.0 V voltage reference) DUTGND (calibrated for 0.0 A current reference) DUTGND Rev Page ADATE302-02 ...
Page 46
... ADATE302-02 Table 25. PMU Measure Enable (ADDR[4:0] = 0x0F) Bit Name Data[2:1] MEASOUT01 select Data[0] MEASOUT01 output enable 1 This register is written to or read from if either of the CH[1:0] bits is 1. Table 26. Differential Comparator Enable (ADDR[4:0] = 0x10) Bit Name Data[0] Differential comparator enable 1 This register is written to or read from if either of the CH[1:0] bits is 1. ...
Page 47
... Logic low: VOL0 > V DUT0 DUT0 Differential comparator mode − V Logic high: VOL0 < V − V DUT0 DUT1 DUT0 − V Logic low: VOL0 > V − V DUT0 DUT1 DUT0 Rev Page ADATE302-02 Signals DATAx RCVx Driver State X X High-Z without clamps High-Z with ...
Page 48
... ADATE302-02 DETAILS OF DACs vs. LEVELS There are ten 14-bit DACs per channel. These DACs provide levels for the driver, comparator, load currents, VHH buffer, OVD, and clamp levels. There are three versions of output levels: • −2 +7.5 V; tracks DUTGND. Controls VH, VL, VT/VCOM/VHH, VOH, VOL, VCH, and VCL levels. ...
Page 49
... HVOUT mode disabled, load disabled, VTERM inactive 0x0000: input of DUTGND, internal sense, clamps disabled, FVMV, Range E 0x0000: MEASOUT01 pin tristated 0x0000: normal window comparator mode 0x0000: DAC16_MON tristated 0x0000: disable alarm functions Logic low Logic low Unterminated Unterminated Rev Page ADATE302-02 ...
Page 50
... ADATE302-02 RECOMMENDED PMU MODE SWITCHING SEQUENCES To minimize any possible aberrations and voltage spikes on the DUT output, specific mode switching sequences are recommended for the following transitions: • PMU disable to PMU enable • PMU force voltage mode to PMU force current mode • ...
Page 51
... X Data[6] X Data[5] X Data[4] X Data[3] 1 Data[2:0] XXX Rev Page ADATE302-02 Comments Set 2 input selection DUTGND Set to force current mode 2 μA range has the minimum offset current Comments Update the PMUDAC level register to the desired value Comments PMUDAC input selection Set to force current mode ...
Page 52
... ADATE302-02 Transition from PMU Force Current Mode to PMU Force Voltage Mode Step 1: See Table 46 for state of registers in force current mode. Table 46. Register PE/PMU Enable Register, ADDR[4:0] = 0x0C PMU State Register, ADDR[4:0] = 0x0E Step 2: Write to Register ADDR[4:0] = 0x0E (see Table 47). Table 47. ...
Page 53
... VH 48Ω VL DATA RCV (SHOWN IN RCV = 0 STATE) HV MODE SELECT DATA[2] (ADDR [4:0] = 0x0D) DISABLES HV DRIVER AND FORCES 0V ON HVOUT WHEN 0 Figure 89. HVOUT Driver Output Stage Rev Page ADATE302-02 PE DISABLE DATA[0] (ADDR[4:0] = 0x0C) FORCES SWITCH OPEN WHEN 48Ω OUT (TRIMMED) DUT HVOUT ...
Page 54
... ADATE302-02 DUT0 DUT1 DIFFERENTIAL NOTES 1. DIFFERENTIAL COMPARATOR ONLY ON CHANNEL 0. VOH0 – VOH NWC + 2:1 + MUX VOL NWC VOL0 – VOH0 – VOH DMC 2:1 + MUX DUT0– – DUT1 BUFFER VOL VOL0 DMC – Figure 90. Comparator Block Diagram COMP_VTT COMP_QP 50Ω ...
Page 55
... REF MUX 225kΩ 2µA 20µA 330pF SCAP (ADDR[4:0] = 0x0E) (EXTERNAL) VCH VCL Figure 92. PMU Block Diagram Rev Page ADATE302-02 10kΩ 2.5 + DUTGND DUT 22.5kΩ 2.25kΩ 250Ω 200µA 2mA FFCAP_A FFCAP_B 25mA BUFFER CRA = 220pF 25mA 20Ω ...
Page 56
... DATA[0] OVD MASK ENABLES OVD FLAGS TO ALARM OVD_CHx PIN 1 6.5V 1 (ADDR[4:0] = 0x12) DATA[1] PMU MASK ENABLES PMU V/I FLAG TO ALARM OVD_CHx PIN 2 (ADDR[4:0] = 0x13) DATA[2] DATA[1] DATA[0] Figure 93. OVD Block Diagram Rev Page OVD_CHx SHORT CIRCUIT CURRENT = 100µA ADATE302-02 ...
Page 57
... MAX 0.60 14.00 BSC SQ 0.45 100 1 PIN 1 EXPOSED PAD TOP VIEW (PINS DOWN 0.50 BSC VIEW A LEAD PITCH COMPLIANT TO JEDEC STANDARDS MS-026-AED-HU Figure 95. 100-Lead Thin Quad Flatpack, Exposed Pad [TQFP_EP] (SV-100-7) Dimensions shown in millimeters Rev Page ADATE302-02 A1 BALL CORNER BOTTOM VIEW 0 ...
Page 58
... ADATE302-02 ORDERING GUIDE Model Temperature Range 1 ADATE302-02BBCZ −40°C to +85°C ADATE302-02BSVZ 1 −40°C to +85° RoHS Compliant Part. ©2008–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Package Description 84-Ball Chip Scale Package Ball Grid Array [CSP_BGA] ...