ADATE302-02BSVZ Analog Devices Inc, ADATE302-02BSVZ Datasheet - Page 45

• Manufacturer Part Number: ADATE302-02BSVZ
• Description: Dual DCL With DAC Levels & PMU
• Manufacturer: Analog Devices Inc
• Type: DCLr

Specifications of ADATE302-02BSVZ

• Applications: Automatic Test Equipment
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DETAILS OF REGISTERS
Table 22. PE/PMU Enable (ADDR[4:0] = 0x0C)
Bit
Data[2]
Data[1]
Data[0]
Table 23. Channel State (ADDR[4:0] = 0x0D)
Bit
Data[2]
Data[1]
Data[0]
Table 24. PMU State (ADDR[4:0] = 0x0E)
Bit
Data[9:8]
Data[7]
Data[6]
Data[5]
Data[4]
Data[3]
Data[2:0]
1
2
Note that when the ADDR[4:0] = 0x0C PMU enable bit (Data[2]) = 0, the PMU force outputs and clamps are disabled, and the PMU is placed into measure voltage
mode. Data[9:8] and Data[6:0] of the PMU state register are ignored, and only Data[7], the PMU sense path bit, is valid.
X = don’t care.
Name
PMU input selection
PMU sense path
Reserved
PMU clamp enable
PMU measure V/I
PMU force V/I
PMU range
Name
PMU enable
Force VT
PE disable
Name
HVOUT mode select
Load enable
Driver high-Z/VT
Description
00 = V
01 = 2.5 V + V
1X = PMUDAC
0 = internal sense
1 = external sense
0 = disable clamps
1 = enable clamps
0 = measure voltage mode
1 = measure current mode
0 = force voltage mode
1 = force current mode
0XX = Range E (2 μA)
100 = Range D (20 μA)
101 = Range C (200 μA)
110 = Range B (2 mA)
111 = Range A (25 mA)
0 = enable driver functions
Description
0 = disable PMU force output and clamps, place PMU in MV mode
1 = enable PMU force output
When set to 0, the PMU State bits are ignored, except for PMU Sense Path (Data[7]).
0 = normal driver operation
1 = force driver to V
See Table 30 for complete functionality of this bit.
1 = disable driver (low leakage)
See Table 30 for complete functionality of this bit.
Description
0 = HVOUT driver in low impedance
1 = enable HVOUT driver
This bit affects Channel 0 only. Ensure that Channel 0 bit in SPI write is active.
Channel 1 bit in SPI write is don’t care.
0 = disable load
1 = enable load
See Table 30 for complete functionality of this bit.
0 = enable driver high-Z function
1 = enable driver VTERM function
See Table 30 for complete functionality of this bit.
DUTGND
1, 2
(calibrated for 0.0 V voltage reference)
DUTGND
(calibrated for 0.0 A current reference)
T
Rev. A | Page 45 of 58
ADATE302-02