ADE7166ASTZF16-RL Analog Devices Inc, ADE7166ASTZF16-RL Datasheet - Page 44
![IC,Power Metering,QFP,64PIN,PLASTIC](/photos/6/60/66065/505-64-lqfp_sml.jpg)
ADE7166ASTZF16-RL
Manufacturer Part Number
ADE7166ASTZF16-RL
Description
IC,Power Metering,QFP,64PIN,PLASTIC
Manufacturer
Analog Devices Inc
Datasheet
1.ADE7169ASTZF16.pdf
(152 pages)
Specifications of ADE7166ASTZF16-RL
Applications
Energy Measurement
Core Processor
8052
Program Memory Type
FLASH (16 kB)
Controller Series
ADE71xx
Ram Size
512 x 8
Interface
I²C, SPI, UART
Number Of I /o
20
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADE7166ASTZF16-RL
Manufacturer:
KOA
Quantity:
50 000
Company:
Part Number:
ADE7166ASTZF16-RL
Manufacturer:
Analog Devices Inc
Quantity:
10 000
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Address
MADDPT[6:0]
0x25
0x26
0x27
0x28
0x29
0x2A
0x3B
0x3C
0x3D
0x3E
0x3F
1
2
ENERGY MEASUREMENT INTERNAL REGISTER DETAILS
Table 33. MODE1 Register (MODE1, Address 0x0B)
Bit
7
6
5
4
3
2
1
0
Table 34. MODE2 Register (MODE2, Address 0x0C)
Bit
[7:6]
[5:4]
3
2
This function is not available in the ADE7116, ADE7156, ADE7166, or ADE7566.
This function is not available in the ADE7566 or ADE7569.
Mnemonic
SWRST
DISZXLPF
INTE
SWAPBITS
PWRDN
DISCF2
DISCF1
DISHPF
Mnemonic
CF2SEL
CF1SEL
VARMSCFCON
ZXRMS
Mnemonic
VARDIV
VADIV
CF1NUM
CF1DEN
CF2NUM
CF2DEN
Reserved
Reserved
CALMODE
Reserved
Reserved
Default
0
0
0
0
0
1
1
0
2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
01
00
0
0
Description
Setting this bit resets all of the energy measurement registers to their default values.
Setting this bit disables the zero-crossing low-pass filter.
Setting this bit enables the digital integrator for use with a di/dt sensor.
Setting this bit swaps CH1 ADC and CH2 ADC.
Setting this bit powers down voltage and current ADCs.
Setting this bit disables Frequency Output CF2.
Setting this bit disables Frequency Output CF1.
Setting this bit disables the HPFs in voltage and current channels.
Length
(Bits)
8
8
16
16
16
16
8
Signed/
Unsigned
U
U
U
U
U
U
U
Description
Configuration bits for CF2 output.
CF2SEL
00
01
1X
Configuration bits for CF1 output.
CF1SEL
00
01
1X
Configuration bits for apparent power or I
(VAHR, RVAHR, and LVAHR). Note that CF1 cannot be proportional to VA if CF2 is proportional to
I
VARMSCFCON
0
1
Logic 1 enables update of rms values synchronously to Voltage ZX.
rms
, and vice versa.
Default
0
0
0
0x003F
0
0x003F
0
0x0300
0
0
0
Rev. B | Page 44 of 152
Result
CF2 frequency is proportional to active power.
CF2 frequency is proportional to reactive power.
CF2 frequency is proportional to apparent power or I
Result
CF1 frequency is proportional to active power.
CF1 frequency is proportional to reactive power.
CF1 frequency is proportional to apparent power or I
Result
If CF1SEL[1:0] = 1X, CF1 is proportional to VA.
If CF2SEL[1:0] = 1X, CF2 is proportional to VA.
If CF1SEL[1:0] = 1X, CF1 is proportional to I
If CF2SEL[1:0] = 1X, CF2 is proportional to I
Description
Sets var energy scaling register.
Sets VA energy scaling register.
Sets CF1 numerator register.
Sets CF2 numerator register.
Sets CF2 denominator register.
This register must be set to its default value for proper operation.
This register must be set to its default value for proper operation.
Set calibration mode.
This register must be set to its default value for proper operation.
This register must be set to its default value for proper operation.
Sets CF1 denominator register.
rms
for CF1, CF2 outputs and VA accumulation registers
rms
rms
.
.
1
1
rms
rms
.
.