ADF4112BRU Analog Devices Inc, ADF4112BRU Datasheet - Page 4
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ADF4112BRU
Manufacturer Part Number
ADF4112BRU
Description
Phase Lock Loop (PLL) IC
Manufacturer
Analog Devices Inc
Type
Clock/Frequency Synthesizer (RF)r
Datasheet
1.ADF4113BRUZ.pdf
(28 pages)
Specifications of ADF4112BRU
Peak Reflow Compatible (260 C)
No
Leaded Process Compatible
No
Rohs Status
RoHS non-compliant
Pll
Yes
Input
Clock
Output
Clock
Number Of Circuits
1
Ratio - Input:output
2:1
Differential - Input:output
Yes/No
Frequency - Max
3GHz
Divider/multiplier
Yes/No
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-TSSOP
Frequency-max
3GHz
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
EVAL-ADF4112EBZ1 - BOARD EVAL FOR ADF4112EVAL-ADF411XEBZ1 - BOARD EVAL FOR ADF411X NO CHIP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADF4112BRU
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
ADF4112BRUZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
ADF4112BRUZ-REEL
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Company:
Part Number:
ADF4112BRUZ-REEL7
Manufacturer:
TriQuin
Quantity:
101
Part Number:
ADF4112BRUZ-REEL7
Manufacturer:
ADI/亚德诺
Quantity:
20 000
ADF4110/ADF4111/ADF4112/ADF4113
Parameter
POWER SUPPLIES
NOISE CHARACTERISTICS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
The B chip specifications are given as typical values.
This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that
AC coupling ensures AV
Guaranteed by design.
is less than this value.
T
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO, PN
value) and 10logF
The phase noise is measured with the EVAL-ADF411xEB1 evaluation board and the HP8562E spectrum analyzer. The spectrum analyzer provides the REFIN for the
synthesizer (f
f
f
REFIN
REFIN
f
f
f
f
f
A
REFIN
REFIN
REFIN
REFIN
REFIN
AV
DV
V
I
Low Power Sleep Mode
ADF4113 Normalized Phase Noise Floor
Phase Noise Performance
Spurious Signals
DD
= 25°C; AV
P
5
ADF4110
ADF4111
ADF4112
ADF4113
I
ADF4110: 540 MHz Output
ADF4111: 900 MHz Output
ADF4112: 900 MHz Output
ADF4113: 900 MHz Output
ADF4111: 836 MHz Output
ADF4112: 1750 MHz Output
ADF4112: 1750 MHz Output
ADF4112: 1960 MHz Output
ADF4113: 1960 MHz Output
ADF4113: 3100 MHz Output
ADF4110: 540 MHz Output
ADF4111: 900 MHz Output
ADF4112: 900 MHz Output
ADF4113: 900 MHz Output
ADF4111: 836 MHz Output
ADF4112: 1750 MHz Output
ADF4112: 1750 MHz Output
ADF4112: 1960 MHz Output
ADF4113: 1960 MHz Output
ADF4113: 3100 MHz Output
= 10 MHz; f
= 10 MHz; f
DD
DD
P
= 10 MHz; f
= 10 MHz; f
= 10 MHz; f
= 10 MHz; f
= 10 MHz; f
(AI
DD
+ DI
DD
REFOUT
= DV
PFD
PFD
DD
PFD
PFD
PFD
PFD
PFD
PFD
)
= 10 MHz @ 0 dBm). SYNC = 0; DLY = 0 (Ta
= 200 kHz; offset frequency = 1 kHz; f
= 200 kHz; offset frequency = 1 kHz; f
= 30 kHz; offset frequency = 300 Hz; f
= 200 kHz; offset frequency = 1 kHz; f
= 10 kHz; offset frequency = 200 Hz; f
= 200 kHz; offset frequency = 1 kHz; f
= 1 MHz; offset frequency = 1 kHz; f
DD
: PN
= 3 V; P = 16; SYNC = 0; DLY = 0; RF
DD
SYNTH
/2 bias. See Figure 33 for a typical circuit.
= PN
7
TOT
8
9
9
9
10
9
9
9
9
10
11
12
13
14
13
11
12
13
13
14
– 10logF
PFD
6
– 20logN.
B Version
2.7/5.5
AV
AV
5.5
5.5
7.5
11
0.5
1
−215
−91
−87
−90
−91
−78
−86
−66
−84
−85
−86
−97/−106
−98/−110
−91/−100
−100/−110
−81/−84
−88/−90
−65/−73
−80/−84
−80/−84
−80/−82
DD
DD
RF
RF
RF
RF
RF
RF
RF
= 3100 MHz; N = 3100; loop B/W = 20 kHz.
/6.0
IN
= 540 MHz; N = 2700; loop B/W = 20 kHz.
= 900 MHz; N = 4500; loop B/W = 20 kHz.
= 836 MHz; N = 27867; loop B/W = 3 kHz.
= 1750 MHz; N = 8750; loop B/W = 20 kHz
= 1750 MHz; N = 175000; loop B/W = 1 kHz.
= 1960 MHz; N = 9800; loop B/W = 20 kHz.
for ADF4110 = 540 MHz; RF
ble 7
).
B Chips
2.7/5.5
AV
AV
4.5
4.5
6.5
8.5
0.5
−215
−91
−87
−90
−91
−78
−86
−66
−84
−85
−86
−97/−106
−98/−110
−91/−100
−100/−110
−81/−84
−88/−90
−65/−73
−80/−84
−80/−84
−82/−82
1
DD
DD
Rev. C | Page 4 of 28
/6.0
1
Unit
V min/V max
V min/V max
mA max
mA max
mA max
mA max
mA max
µA typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
dBc typ
IN
for ADF4111, ADF4112, ADF4113 = 900 MHz.
Test Conditions/Comments
AV
4.5 mA typical
4.5 mA typical
6.5 mA typical
8.5 mA typical
T
@ VCO output
@ 1 kHz offset and 200 kHz PFD frequency
@ 1 kHz offset and 200 kHz PFD frequency
@ 1 kHz offset and 200 kHz PFD frequency
@ 1 kHz offset and 200 kHz PFD frequency
@ 300 Hz offset and 30 kHz PFD frequency
@ 1 kHz offset and 200 kHz PFD frequency
@ 200 Hz offset and 10 kHz PFD frequency
@ 1 kHz offset and 200 kHz PFD frequency
@ 1 kHz offset and 200 kHz PFD frequency
@ 1 kHz offset and 1 MHz PFD frequency
@ 200 kHz/400 kHz and 200 kHz PFD frequency
@ 200 kHz/400 kHz and 200 kHz PFD frequency
@ 200 kHz/400 kHz and 200 kHz PFD frequency
@ 200 kHz/400 kHz and 200 kHz PFD frequency
@ 30 kHz/60 kHz and 30 kHz PFD frequency
@ 200 kHz/400 kHz and 200 kHz PFD frequency
@ 10 kHz/20 kHz and 10 kHz PFD frequency
@ 200 kHz/400 kHz and 200 kHz PFD frequency
@ 200 kHz/400 kHz and 200 kHz PFD frequency
@ 1 MHz/2 MHz and 1 MHz PFD frequency
A
= 25°C
DD
≤ V
TOT
P
≤ 6.0 V. See Figure 25 and Figure 26.
, and subtracting 20logN (where N is the N divider