ADF4112BRU Analog Devices Inc, ADF4112BRU Datasheet - Page 5
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ADF4112BRU
Manufacturer Part Number
ADF4112BRU
Description
Phase Lock Loop (PLL) IC
Manufacturer
Analog Devices Inc
Type
Clock/Frequency Synthesizer (RF)r
Datasheet
1.ADF4113BRUZ.pdf
(28 pages)
Specifications of ADF4112BRU
Peak Reflow Compatible (260 C)
No
Leaded Process Compatible
No
Rohs Status
RoHS non-compliant
Pll
Yes
Input
Clock
Output
Clock
Number Of Circuits
1
Ratio - Input:output
2:1
Differential - Input:output
Yes/No
Frequency - Max
3GHz
Divider/multiplier
Yes/No
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-TSSOP
Frequency-max
3GHz
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
EVAL-ADF4112EBZ1 - BOARD EVAL FOR ADF4112EVAL-ADF411XEBZ1 - BOARD EVAL FOR ADF411X NO CHIP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADF4112BRU
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
ADF4112BRUZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
ADF4112BRUZ-REEL
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Company:
Part Number:
ADF4112BRUZ-REEL7
Manufacturer:
TriQuin
Quantity:
101
Part Number:
ADF4112BRUZ-REEL7
Manufacturer:
ADI/亚德诺
Quantity:
20 000
TIMING CHARACTERISTICS
Guaranteed by design but not production tested. AV
AGND = DGND = CPGND = 0 V; R
Table 2.
Parameter
t
t
t
t
t
t
1
2
3
4
5
6
CLOCK
DATA
LE
LE
DB20 (MSB)
Limit at T
10
10
25
25
10
20
MIN
SET
to T
= 4.7 kΩ; T
t
1
MAX
DB19
(B Version)
t
2
A
DD
= T
= DV
MIN
Figure 2. Timing Diagram
to T
DD
Rev. C | Page 5 of 28
= 3 V ± 10%, 5 V ± 10%; AV
DB2
MAX
t
3
, unless otherwise noted.
Unit
ns min
ns min
ns min
ns min
ns min
ns min
t
4
(CONTROL BIT C2)
ADF4110/ADF4111/ADF4112/ADF4113
DB1
Test Conditions/Comments
DATA to CLOCK setup time
DATA to CLOCK hold time
CLOCK high duration
CLOCK low duration
CLOCK to LE setup time
LE pulse width
DD
≤ V
P
≤ 6 V;
(CONTROL BIT C1)
DB0 (LSB)
t
5
t
6