ADF7011BRU-REEL Analog Devices Inc, ADF7011BRU-REEL Datasheet - Page 5

• Manufacturer Part Number: ADF7011BRU-REEL
• Description: IC,RF Modulator,CMOS,TSSOP,24PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of ADF7011BRU-REEL

• Rohs Status: RoHS non-compliant
• Frequency: 433 ~ 435MHz; 866 ~ 870MHz
• Applications: Data Transfer, RKE, Remote Control/Security Systems
• Modulation Or Protocol: ASK, FSK, GFSK, OOK
• Data Rate - Maximum: 76.8 kbps
• Power - Output: -16dBm ~ 12dBm
• Current - Transmitting: 34mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 2.3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 24-TSSOP
• Features: -
• Memory Size: -

Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
REV. 0
Mnemonic
R
CPV
CP
CP
CE
DATA
CLK
LE
TxDATA
TxCLK
MUXOUT
D
CLK
OSC2
SET
GND
GND
OUT
DD
OUT
Function
External Resistor to Set Change Pump Current and Some Internal Bias Currents. Use 4.7 kΩ as default:
So, with R
Charge Pump Supply. This should be biased at the same level as RF
decoupled with a 0.1 µF capacitor as close to the pin as possible.
Charge Pump Ground.
Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The
integrated current changes the control voltage on the input to the VCO.
Chip Enable. A logic low applied to this pin powers down the part. This must be high for the part to
function. This is the only way to power down the regulator circuit.
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This is a
high impedance CMOS input.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched
into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one
of the four latches, the latch being selected using the control bits.
Digital data to be transmitted is input on this pin.
GFSK Only. This clock output is used to synchronize microcontroller data to the TxDATA pin of the
ADF7011. The clock is provided at the same frequency as the data rate.
This multiplexer output allows either the digital lock detect (most common), the scaled RF, or the scaled
reference frequency to be accessed externally. Used commonly for system debug. See the Function Regis-
ter Map.
Ground Pin for the RF Digital Circuitry.
The Divided Down Crystal Reference with 50:50 Mark-Space Ratio. May be used to drive the clock
input of a microcontroller. To reduce spurious components in the output spectrum, the sharp edges can
be reduced with a series RC. For 4.8 MHz output clock, a series 50 Ω into 10 pF will reduce spurs to
< –50 dBc. Defaults on power-up to divide by 16.
Oscillator Pin. If a single-ended reference (such as a TCXO) is used, it should be applied to this pin.
When using an external signal generator, a 51 Ω resistor should be tied from this pin to ground. The
XOE bit in the R register should set high when using an external reference.
I
CP MAX
=
SET
R
9 5 .
SET
= 4.7 kΩ, I
PIN FUNCTION DESCRIPTIONS
MUXOUT
CP MAX
TxDATA
CPV
CP
TxCLK
CP
PIN CONFIGURATION
D
DATA
R
CLK
GND
GND
OUT
SET
CE
LE
DD
10
11
12
= 2.02 mA.
1
2
3
4
5
6
7
8
9
ADF7011
(Not to Scale)
TOP VIEW
TSSOP
–5–
24
23
22
21
20
19
18
17
16
15
14
13
CLK
C
C
VCO
A
RF
RF
DV
TEST
VCO
OSC1
OSC2
REG
VCO
GND
OUT
GND
DD
OUT
IN
GND
OUT
and DV
DD
. The pin should be
ADF7011