ADM8696ANZ Analog Devices Inc, ADM8696ANZ Datasheet - Page 4

• Manufacturer Part Number: ADM8696ANZ
• Description: IMPROVED ADM696 I.C.
• Manufacturer: Analog Devices Inc
• Type: Battery Backup Circuitr

Specifications of ADM8696ANZ

• Number Of Voltages Monitored: 1
• Output: Push-Pull, Push-Pull
• Reset: Active High/Active Low
• Reset Timeout: 35 ms Minimum
• Voltage - Threshold: 1.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 16-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADM8696/ADM8697
Mnemonic
V
V
V
GND
RESET
WDI
PFI
PFO
CE
CE
BATT ON
LOW LINE 6
RESET
OSC SEL
OSC IN
WDO
NC
LL
TEST
CC
BATT
OUT
IN
IN
OUT
ADM8696 ADM8697 Function
3
1
2
4
15
11
9
10
—
—
5
16
8
7
14
12
13
—
Pin No.
3
—
—
5
15
11
9
10
13
12
—
6
16
8
7
14
2
4
1
0 V. Ground reference for all signals.
Watchdog Input, WDI is a three level input. If WDI remains either high or low for longer
Power Fail Input. PFI is the noninverting input to the Power Fail Comparator when PFI is
Logic Output. RESET is an active high output. It is the inverse of RESET.
No Connect. It should be left open.
This is a special test pin using during device manufacture. It should be connected to GND.
Power Supply Input +3 V to +5 V.
Backup Battery Input.
Output Voltage, V
the highest potential. When V
threshold, V
reset threshold, V
RAM. Connect V
Logic Output. RESET goes low whenever LL
after LL
abled but not serviced within its timeout period. The RESET pulse width can be adjusted as
shown in Table I.
than the watchdog timeout period, RESET pulses low and WDO goes low. The timer resets
with each transition at the WDI input. The watchdog timer is disabled when WDI is left
floating or is driven to midsupply.
less than 1.3 V, PFO goes low. Connect PFI to GND or V
Power Fail Output. PFO is the output of the Power Fail Comparator. It goes low when PFI
is less than 1.3 V. The comparator is turned off and PFO goes low when V
V
Logic Input. The input to the CE gating circuit. Connect to GND or V
Logic Output. CE
is above 1.3 V. If LL
Logic Output. BATT ON goes high when V
It goes low when V
can directly drive the base of an external PNP transistor to increase the output current above
the 100 mA rating of V
Logic Output. LOW LINE goes low when LL
LL
Logic Oscillator Select Input. When OSC SEL is unconnected or driven high, the internal
oscillator sets the reset time delay and watchdog timeout period. When OSC SEL is low, the
external oscillator input, OSC IN, is enabled. OSC SEL has a 3 A internal pull-up. See
Table I and Figure 4.
Logic Oscillator Input. When OSC SEL is low, OSC IN can be driven by an external clock
to adjust both the reset delay and the watchdog timeout period. The timing can also be
adjusted by connecting an external capacitor to this pin. See Table I and Figure 4. When
OSC SEL is high or floating, OSC IN selects between fast and slow watchdog timeout periods.
Logic Output. The Watchdog Output, WDO, goes low if WDI remains either high or low
for longer than the watchdog timeout period. WDO is set high by the next transition at
WDI. If WDI is unconnected or at midsupply, WDO remains high. WDO also goes high
when LOW LINE goes low.
Voltage Sensing Input. The voltage on the low line input, LL
reference voltage. This input is normally used to monitor the power supply voltage. The
output of the comparator generates a LOW LINE output signal. It also generates a
RESET/RESET output. The comparator output also controls the battery switchover circuitry.
BATT
IN
rises above 1.3 V.
.
IN
PIN FUNCTION DESCRIPTION
goes above 1.3 V. RESET also goes low for 50 ms if the watchdog timer is en-
CC
is switched to V
BATT
OUT
OUT
CC
OUT
IN
to V
or V
is a gated version of the CE
is switched to V
OUT
is below 1.3 V, CE
is internally switched to V
–4–
CC
BATT
.
if V
CC
OUT
is internally switched to V
OUT
is higher than V
. When V
and V
OUT
OUT
. V
BATT
CC
OUT
OUT
IN
IN
is forced high.
is lower than V
falls below 1.3 V and remains low for 50 ms
are not used.
falls below 1.3 V. It returns high as soon as
is internally switched to the V
CC
can supply up to 100 mA to power CMOS
IN
BATT
. The output typically sinks 7 mA and
signal. CE
and LL
OUT
OUT
IN
BATT
when not used. See Figure 1.
OUT
, is compared with a 1.3 V
depending on which is at
IN
is higher than the reset
tracks CE
and LL
OUT
CC
IN
if not used.
IN
is below the
is below
BATT
when LL
input.
REV. A
IN