ADP1870ACPZ-0.3-R7 Analog Devices Inc, ADP1870ACPZ-0.3-R7 Datasheet
ADP1870ACPZ-0.3-R7
Specifications of ADP1870ACPZ-0.3-R7
ADP1870ACPZ-0.3-R7TR
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ADP1870ACPZ-0.3-R7 Summary of contents
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FEATURES Power input voltage range: 2. On-board bias regulator Minimum output voltage: 0.6 V 0.6 V reference voltage with ±1.0% accuracy Supports all N-channel MOSFET power stages Available in 300 kHz, 600 kHz, and 1.0 MHz ...
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ADP1870/ADP1871 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Typical Applications Circuit ............................................................ 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Absolute Maximum Ratings ............................................................ 5 Thermal Resistance ...................................................................... 5 Boundary Condition .................................................................... 5 ESD ...
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SPECIFICATIONS All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC − − V (see Figure 40 to Figure 42). V BST SW REG RECT_DROP unless otherwise specified. Table 1. ...
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ADP1870/ADP1871 Parameter Symbol ADP1870ARMZ-0.6/ ADP1871ARMZ-0.6 (600 kHz) On-Time Minimum On-Time Minimum Off-Time ADP1870ARMZ-1.0/ ADP1871ARMZ-1.0 (1.0 MHz) On-Time Minimum On-Time Minimum Off-Time OUTPUT DRIVER CHARACTERISTICS High-Side Driver Output Source Resistance Output Sink Resistance 2 Rise Time t r,DRVH 2 Fall Time ...
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ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating VREG to PGND, GND −0 VIN to PGND −0 +28 V FB, COMP/EN to GND −0 DRVL to PGND −0 ...
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ADP1870/ADP1871 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 VIN High Input Voltage. Connect VIN to the drain of the upper-side MOSFET. 2 COMP/EN Output of the Internal Error Amplifier/IC Enable. When this ...
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TYPICAL PERFORMANCE CHARACTERISTICS 100 13V (PSM 13V 25° 16.5V (PSM 0.8V OUT ...
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ADP1870/ADP1871 100 13V 13V (PSM 25° 0.8V OUT V = 16.5V (PSM ...
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V = 13V IN +25° 16.5V IN –40°C 0.792 0 1000 2000 3000 4000 5000 6000 7000 8000 LOAD CURRENT (mA) Figure 16. Output Voltage Accuracy—600 kHz, V 1.818 ...
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ADP1870/ADP1871 601.0 600 5V 20V REG IN 600.0 599 5V 13V REG IN 599.0 598.5 598.0 597.5 597.0 –40.0 –7.5 25.0 57.5 TEMPERATURE (°C) Figure 22. Feedback Voltage vs. Temperature 325 +125°C ...
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V = 13V +125°C IN +25° 16.5V 334 IN –40°C 330 326 322 318 314 310 306 302 298 0 800 1600 2400 3200 4000 4800 5600 6400 7200 8000 8800 LOAD CURRENT (mA) Figure 28. Frequency ...
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ADP1870/ADP1871 1450 V = 13V +125°C IN +25° 16.5V IN 1400 –40°C 1350 1300 1250 1200 1150 1100 1050 1000 0 800 1600 2400 3200 4000 4800 5600 6400 7200 LOAD CURRENT (mA) Figure 34. Frequency vs. Load ...
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V = 2.7V +125°C REG +25° 3.6V REG 720 –40° 5.5V REG 640 560 480 400 320 240 160 80 300 400 500 600 700 800 FREQUENCY (kHz) Figure 40. Internal Rectifier Drop vs. Frequency ...
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ADP1870/ADP1871 OUTPUT VOLTAGE 4 INDUCTOR CURRENT 1 SW NODE 3 CH1 5A Ω M400ns B CH3 10V CH4 100mV T 30.6% W Figure 46. CCM Operation at Heavy Load (See Figure 94 for Application Circuit) OUTPUT VOLTAGE 2 ...
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OUTPUT VOLTAGE 2 12A NEGATIVE STEP 1 SW NODE 3 LOW SIDE 4 CH1 10A Ω B CH2 200mV M10µs W CH3 20V CH4 5V T 23.8% Figure 52. Negative Step During Heavy Load Transient Behavior—Forced PWM at Light Load, ...
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ADP1870/ADP1871 OUTPUT VOLTAGE 1 LOW SIDE 4 SW NODE 3 INDUCTOR CURRENT 2 B CH2 5A Ω CH1 1V M1ms W B CH3 10V CH4 2V T 63.2% W Figure 58. Soft Start and RES Detect Waveform T = 25°C ...
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V (V) REG Figure 64. Quiescent Current vs. V 5.1 5.5 REG Rev Page 17 of ...
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ADP1870/ADP1871 ADP1870/ADP1871 BLOCK DIAGRAM ADP1870/ADP1871 PRECISION ENABLE BLOCK VREG REF_ZERO COMP C SS SS_REF COMP/ EN ERROR AMP FB 0.6V LOWER COMP CLAMP REF_ZERO VREG t TIMER ENABLE ALL BLOCKS I LDO SW INFORMATION ...
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THEORY OF OPERATION The ADP1870/ADP1871 are versatile current-mode, synchronous step-down controllers that provide superior transient response, optimal stability, and current limit protection by using a constant on-time, pseudo-fixed frequency with a programmable current- sense gain, current-control scheme. In addition, these ...
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ADP1870/ADP1871 VIN and VREG be tied together if the VIN pin is subjected to a 2.75 V rail. Table 5. Power Input and LDO Output Configurations VIN VREG Comments >5.5 V Float Must use the LDO <5.5 V Connect to ...
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When the desired valley current limit (I CLIM the current-sense gain can be calculated as follows CLIM × where the channel impedance of the lower-side MOSFET ...
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ADP1870/ADP1871 SYNCHRONOUS RECTIFIER The ADP1870/ADP1871 employ an internal lower-side MOSFET driver to drive the external upper- and lower-side MOSFETs. The synchronous rectifier not only improves overall conduction efficiency, but also ensures proper charging to the bootstrap capacitor located at the ...
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VREG INFORMATION R Figure 77. Constant On-Time Time The constant on-time ( not strictly “constant” because it ON varies with V and V . However, this variation occurs in such IN OUT a ...
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ADP1870/ADP1871 APPLICATIONS INFORMATION FEEDBACK RESISTOR DIVIDER The required resistor divider network can be determined for a given V value because the internal band gap reference (V OUT is fixed at 0.6 V. Selecting values for R T minimum output load ...
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Ceramic capacitors are known to have low ESR. However, the trade-off of using X5R technology is that up to 80% of its capaci- tance might be lost due to derating as the voltage applied across the capacitor is increased (see ...
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ADP1870/ADP1871 EFFICIENCY CONSIDERATIONS One of the important criteria to consider in constructing a dc-to-dc converter is efficiency. By definition, efficiency is the ratio of the output power to the input power. For high power applications at load currents up to ...
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Diode Conduction Loss The ADP1870/ADP1871 employ anticross conduction circuitry that prevents the upper- and lower-side MOSFETs from conducting current simultaneously. This overlap control is beneficial, avoiding large current flow that may lead to irreparable damage to the external components of ...
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ADP1870/ADP1871 THERMAL CONSIDERATIONS The ADP1870/ADP1871 are used for dc-to-dc, step down, high current applications that have an on-board controller, an on-board LDO, and on-board MOSFET drivers. Because applications may require load current delivery and be ...
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DISS ( LDO ) DR ( LOSS ) IN REG SW where the power dissipated through the pass device in the DISS(LDO) LDO block across ...
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ADP1870/ADP1871 Therefore, an appropriate inductor selection is five 270 μF polymer capacitors with a combined ESR of 3.5 mΩ. Assuming an overshoot of 45 mV, determine if the output capacitor that was calculated previously is adequate: × ...
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EXTERNAL COMPONENT RECOMMENDATIONS The configurations listed in Table 10 are with f (BSC042N03MS G (float), and a maximum load current REG The ADP1871 models listed in Table 10 are the PSM versions of ...
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ADP1870/ADP1871 Marking Code SAP Model ADP1870 LDY LDY 1 See the Inductor Selection section and Table μF Murata 25 V, X7R, 1210 GRM32ER71E226KE15L (3.2 mm × 2.5 mm × 2.5 mm). 3 560 μF Panasonic (SP-series) 2 ...
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LAYOUT CONSIDERATIONS The performance of a dc-to-dc converter depends highly on how the voltage and current paths are configured on the printed circuit board (PCB). Optimizing the placement of sensitive analog and power components is essential to minimize output ripple, ...
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ADP1870/ADP1871 SENSITIVE ANALOG COMPONENTS LOCATED FAR FROM THE NOISY POWER SECTION. SEPARATE ANALOG GROUND PLANE FOR THE ANALOG COMPONENTS (THAT IS, COMPENSATION AND FEEDBACK RESISTORS). BYPASS POWER CAPACITOR (C1) FOR VREG BIAS DECOUPLING AND HIGH FREQUENCY CAPACITOR (C2) AS CLOSE ...
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Figure 87. Layer 2 of Evaluation Board Rev Page ADP1870/ADP1871 ...
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ADP1870/ADP1871 TOP RESISTOR FEEDBACK TAP V SENSE TAP LINE OUT EXTENDING BACK TO THE TOP RESISTOR IN THE FEEDBACK DIVIDER NETWORK (SEE FIGURE 86 TO FIGURE 88). THIS OVERLAPS WITH PGND SENSE TAP LINE EXTENDING BACK TO THE ANALOG PLANE ...
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BOTTOM RESISTOR TAP TO THE ANALOG GROUND PLANE PGND SENSE TAP FROM NEGATIVE TERMINALS OF OUTPUT BULK CAPACITORS. THIS TRACK PLACEMENT SHOULD BE DIRECTLY BELOW THE V LINE FROM FIGURE 84. IC SECTION (LEFT SIDE OF EVALUATION BOARD) A dedicated ...
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ADP1870/ADP1871 (component geometry permitting) that minimizes the area of flux change as the event switches between D and 1 − VIN PGND Figure 90. Primary Current Pathways During the On State of the Upper-Side MOSFET (Left Arrow) and ...
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TYPICAL APPLICATIONS CIRCUITS 15 A, 300 kHz HIGH CURRENT APPLICATION CIRCUIT JP3 C28 10µF C ADP1870/ C 571pF VIN C 1 57pF 47kΩ COMP/ 30kΩ OUT R2 15kΩ GND 4 VREG 5 ...
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ADP1870/ADP1871 300 kHz HIGH CURRENT APPLICATION CIRCUIT JP3 C28 10µF C ADP1870/ C 528pF C R VIN 53pF 43kΩ COMP/ 30kΩ OUT R2 15kΩ GND 4 VREG 0.1µF 1µF ...
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OUTLINE DIMENSIONS IDENTIFIER PIN 1 INDEX AREA 0.80 0.75 0.70 SEATING PLANE 3.10 3.00 2.90 5. 3.10 4.90 3.00 4.65 1 2.90 5 PIN 1 0.50 BSC 0.95 15° MAX 0.85 1.10 MAX 0.75 0.15 0.23 6° 0.30 ...
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... ADP1870ARMZ-1.0-R7 −40°C to +125°C ADP1871ARMZ-0.3-R7 −40°C to +125°C ADP1871ARMZ-0.6-R7 −40°C to +125°C ADP1871ARMZ-1.0-R7 −40°C to +125°C ADP1870ACPZ-0.3-R7 −40°C to +125°C ADP1870ACPZ-0.6-R7 −40°C to +125°C ADP1870ACPZ-1.0-R7 −40°C to +125°C ADP1871ACPZ-0.3-R7 −40°C to +125°C ADP1871ACPZ-0.6-R7 − ...
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NOTES Rev Page ADP1870/ADP1871 ...
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ADP1870/ADP1871 NOTES ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08730-0-6/10(A) Rev Page ...