ADP1870ACPZ-0.3-R7 Analog Devices Inc, ADP1870ACPZ-0.3-R7 Datasheet - Page 37

• Manufacturer Part Number: ADP1870ACPZ-0.3-R7
• Description: 300kHz, Light Load Eff Enabled
• Manufacturer: Analog Devices Inc

Specifications of ADP1870ACPZ-0.3-R7

• Frequency - Max: 300kHz
• Pwm Type: Current Mode
• Number Of Outputs: 1
• Duty Cycle: 84%
• Voltage - Supply: 2.95 V ~ 20 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 10-WFDFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADP1870ACPZ-0.3-R7; ADP1870ACPZ-0.3-R7TR

IC SECTION (LEFT SIDE OF EVALUATION BOARD)
A dedicated plane for the analog ground plane (GND) should
be separate from the main power ground plane (PGND). With
the shortest path possible, connect the analog ground plane to
the GND pin (Pin 4). This plane should be on only the top layer
of the evaluation board. To avoid crosstalk interference, there
should not be any other voltage or current pathway directly
below this plane on Layer 2, Layer 3, or Layer 4. Connect the
negative terminals of all sensitive analog components to the
analog ground plane. Examples of such sensitive analog com-
ponents include the resistor divider’s bottom resistor, the high
frequency bypass capacitor for biasing (0.1 μF), and the
compensation network.
Mount a 1 μF bypass capacitor directly across the VREG pin
(Pin 5) and the PGND pin (Pin 7). In addition, a 0.1 μF should
be tied across the VREG pin (Pin 5) and the GND pin (Pin 4).
POWER SECTION
As shown in Figure 86, an appropriate configuration to localize
large current transfer from the high voltage input (V
output (V
V
power ground plane in between the two. Current transfers from
the input capacitors to the output capacitors, through Q1/Q2,
during the on state (see Figure 90). The direction of this current
IN
plane on the left, the output plane on the right, and the main
OUT
) and then back to the power ground is to put the
BOTTOM RESISTOR
TAP TO THE ANALOG
GROUND PLANE
PGND SENSE TAP FROM
NEGATIVE TERMINALS OF
OUTPUT BULK CAPACITORS.
THIS TRACK PLACEMENT
SHOULD BE DIRECTLY
BELOW THE V
LINE FROM FIGURE 84.
Figure 89. Layer 4 (Bottom Layer) of Evaluation Board
OUT
SENSE
IN
) to the
Rev. A | Page 37 of 44
(yellow arrow) is maintained as Q1/Q2 turns off and Q3/Q4
turns on. When Q3/Q4 turns on, the current direction continues to
be maintained (red arrow) as it circles from the bulk capacitor’s
power ground terminal to the output capacitors, through the
Q3/Q4. Arranging the power planes in this manner minimizes
the area in which changes in flux occur if the current through
Q1/Q2 stops abruptly. Sudden changes in flux, usually at source
terminals of Q1/Q2 and drain terminal of Q3/Q4, cause large
dV/dt’s at the SW node.
The SW node is near the top of the evaluation board. The SW
node should use the least amount of area possible and be away
from any sensitive analog circuitry and components because
this is where most sudden changes in flux density occur. When
possible, replicate this pad onto Layer 2 and Layer 3 for thermal
relief and eliminate any other voltage and current pathways directly
beneath the SW node plane. Populate the SW node plane with
vias, mainly around the exposed pad of the inductor terminal
and around the perimeter of the source of Q1/Q2 and the drain
of Q3/Q4. The output voltage power plane (V
most end of the evaluation board. This plane should be replicated,
descending down to multiple layers with vias surrounding the
inductor terminal and the positive terminals of the output bulk
capacitors. Ensure that the negative terminals of the output
capacitors are placed close to the main power ground (PGND),
as previously mentioned. All of these points form a tight circle
ADP1870/ADP1871
OUT
) is at the right-