ADSP-21261SKBCZ150 Analog Devices Inc, ADSP-21261SKBCZ150 Datasheet - Page 8

• Manufacturer Part Number: ADSP-21261SKBCZ150
• Description: 150 MHz, 32Bit DSP Processor
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-21261SKBCZ150

• Interface: DAI, SPI
• Clock Rate: 150MHz
• Non-volatile Memory: ROM (384 kB)
• On-chip Ram: 128kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 136-CSPBGA
• Device Core Size: 32/40Bit
• Architecture: Super Harvard
• Format: Floating Point
• Clock Freq (max): 150MHz
• Mips: 150
• Device Input Clock Speed: 150MHz
• Ram Size: 128KB
• Program Memory Size: 384KB
• Operating Supply Voltage (typ): 1.2/3.3V
• Operating Supply Voltage (min): 1.14/3.13V
• Operating Supply Voltage (max): 1.26/3.47V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 136
• Package Type: CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-21261
DMA transfers are used to move data to and from internal
memory. Access to the core is also facilitated through the paral-
lel port register read/write functions. The RD, WR, and ALE
(address latch enable) pins are the control pins for the
parallel port.
Timers
The ADSP-21261 has a total of four timers: a core timer able to
generate periodic software interrupts, and three general-
purpose timers that can generate periodic interrupts and be
independently set to operate in one of three modes:
The core timer can be configured to use FLAG3 as a timer
expired output signal, and each general-purpose timer has one
bidirectional pin and four registers that implement its mode of
operation: a 6-bit configuration register, a 32-bit count register,
a 32-bit period register, and a 32-bit pulse width register. A sin-
gle control and status register enables or disables all three
general-purpose timers independently.
Program Booting
The internal memory of the ADSP-21261 boots at system
power-up from an 8-bit EPROM via the parallel port, an SPI
master, an SPI slave, or an internal boot. Booting is determined
by the boot configuration (BOOTCFG1–0) pins. Selection of the
boot source is controlled via the SPI as either a master or slave
device, or it can immediately begin executing from ROM.
Phase-Locked Loop
The ADSP-21261 uses an on-chip phase-locked loop (PLL) to
generate the internal clock for the core. On power-up, the
CLKCFG1
After booting, numerous other ratios can be selected via soft-
ware control. The ratios are made up of software configurable
numerator values from 1 to 32 and software configurable divi-
sor values of 1, 2, 4, 8, and 16.
Power Supplies
The ADSP-21261 has separate power supply connections for the
internal (V
power supplies. The internal and analog supplies must meet the
1.2 V requirement. The external supply must meet the 3.3 V
requirement. All external supply pins must be connected to the
same power supply.
Note that the analog supply pin (A
internal clock generator PLL. To produce a stable clock, it is rec-
ommended that PCB designs use an external filter circuit for the
A
A
mended ferrite chip is the muRata BLM18AG102SN1D). To
reduce noise coupling, the PCB should use a parallel pair of
power and ground planes for V
to connect the bypass capacitors to the analog power (A
ground (A
VDD
VDD
• Pulse waveform generation mode
• Pulse width count/capture mode
• External event watchdog mode
/A
pin. Place the filter components as close as possible to the
VSS
–
VSS
pins. For an example circuit, see
DDINT
0 pins are used to select ratios of 16:1, 8:1, and 3:1.
) pins. Note that the A
), external (V
DDEXT
DDINT
), and analog (A
VDD
VDD
and GND. Use wide traces
) powers the processor’s
and A
Figure
VSS
pins specified
VDD
4. (A recom-
Rev. 0 | Page 8 of 44 | March 2006
/A
VDD
VSS
) and
)
in
ground plane on the board—the A
directly to digital ground (GND) at the chip.
TARGET BOARD JTAG EMULATOR CONNECTOR
Analog Devices DSP Tools product line of JTAG emulators uses
the IEEE 1149.1 JTAG test access port of the ADSP-21261 pro-
cessor to monitor and control the target board processor during
emulation. Analog Devices DSP Tools product line of JTAG
emulators provides emulation at full processor speed, allowing
inspection and modification of memory, registers, and proces-
sor stacks. The processor’s JTAG interface ensures that the
emulator will not affect target system loading or timing.
For complete information on Analog Devices’ SHARC DSP
Tools product line of JTAG emulator operation, see the appro-
priate emulator hardware user’s guide.
DEVELOPMENT TOOLS
The ADSP-21261 is supported by a complete set of
CROSSCORE
including Analog Devices emulators and VisualDSP++
development environment. The same emulator hardware that
supports other SHARC processors also fully emulates the
ADSP-21261.
The VisualDSP++ project management environment lets pro-
grammers develop and debug an application. This environment
includes an easy to use assembler (which is based on an alge-
braic syntax), an archiver (librarian/library builder), a linker, a
loader, a cycle-accurate instruction-level simulator, a C/C++
compiler, and a C/C++ runtime library that includes DSP and
mathematical functions. A key point for these tools is C/C++
code efficiency. The compiler has been developed for efficient
translation of C/C++ code to DSP assembly. The ADSP-21261
SHARC DSP has architectural features that improve the
efficiency of compiled C/C++ code.
The VisualDSP++ debugger has a number of important fea-
tures. Data visualization is enhanced by a plotting package that
offers a significant level of flexibility. This graphical representa-
tion of user data enables the programmer to quickly determine
the performance of an algorithm. As algorithms grow in
†
‡
CROSSCORE is a registered trademark of Analog Devices, Inc.
VisualDSP++ is a registered trademark of Analog Devices, Inc.
V DDINT
Figure 4
HI Z FERRITE
BEAD CHIP
are inputs to the processor and not the analog
®†
software and hardware development tools,
Figure 4. Analog Power Filter Circuit
CLOSE TO A VDD AND A VSS PINS
100nF
LOCATE ALL COMPONENTS
10nF
VSS
pin should connect
1nF
ADSP-21261
A
A
VDD
VSS
®‡