ADSP-21262SBBC-150 Analog Devices Inc, ADSP-21262SBBC-150 Datasheet - Page 29

• Manufacturer Part Number: ADSP-21262SBBC-150
• Description: IC,DSP,32-BIT,CMOS,BGA,136PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-21262SBBC-150

• Interface: DAI, SPI
• Clock Rate: 150MHz
• Non-volatile Memory: ROM (512 kB)
• On-chip Ram: 256kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 136-CSPBGA
• Device Core Size: 32/40Bit
• Architecture: Super Harvard
• Format: Floating Point
• Clock Freq (max): 150MHz
• Mips: 150
• Device Input Clock Speed: 150MHz
• Ram Size: 256KB
• Program Memory Size: 512KB
• Operating Supply Voltage (typ): 1.2/3.3V
• Operating Supply Voltage (min): 1.14/3.13V
• Operating Supply Voltage (max): 1.26/3.47V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 136
• Package Type: CSPBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 31. Serial Ports—Enable and Three-State
1
Table 32. Serial Ports—External Late Frame Sync
1
1
Parameter
Switching Characteristics
t
t
t
Referenced to drive edge.
Parameter
Switching Characteristics
t
t
The t
This figure reflects changes made to support left-justified sample pair mode.
DDTEN
DDTTE
DDTIN
DDTLFSE
DDTENFS
DDTLFSE
and t
DDTENFS
Data Enable from External Transmit SCLK
Data Disable from External Transmit SCLK
Data Enable from Internal Transmit SCLK
Data Delay from Late External Transmit FS or External Receive FS
with MCE = 1, MFD = 0
Data Enable for MCE = 1, MFD = 0
parameters apply to left-justified sample pair mode as well as DSP serial mode, and MCE = 1, MFD = 0.
(DATA CHANNEL A/B)
(DATA CHANNEL A/B)
NOTE: SERIAL PORT SIGNALS (SCLK, FS,
USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P[20:1] PINS.
DAI_P20-1
DAI_P20-1
DAI_P20-1
DAI_P20-1
DAI_P20-1
DAI_P201
(SCLK)
(SCLK)
(FS)
(FS)
1
EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0
LATE EXTERNAL TRANSMIT FS
DRIVE
DRIVE
t
DDTLFSE
t
DDTLFSE
1
Figure 20. External Late Frame Sync
t
t
SFSE/I
SFSE/I
Rev. F | Page 29 of 44 | July 2009
t
DDTENFS
t
DDTENFS
1
1
1
SAMPLE
SAMPLE
DATA CHANNEL
1ST BIT
1ST BIT
t
HDTE/I
t
HDTE/I
DRIVE
DRIVE
A/B) ARE ROUTED TO THE DAI_P[20:1] PINS
t
t
ADSP-21261/ADSP-21262/ADSP-21266
HFSE/I
HFSE/I
1
Min
2
–1
Min
0.5
t
DDTE/I
t
DDTE/I
2ND BIT
2ND BIT
Max
7
Max
7
Unit
ns
ns
ns
Unit
ns
ns