ADSP-2187LBSTZ-210 Analog Devices Inc, ADSP-2187LBSTZ-210 Datasheet - Page 44
![no-image](/images/manufacturer_photos/0/0/57/analog_devices_inc_sml.jpg)
ADSP-2187LBSTZ-210
Manufacturer Part Number
ADSP-2187LBSTZ-210
Description
IC,DSP,16-BIT,CMOS,QFP,100PIN,PLASTIC
Manufacturer
Analog Devices Inc
Series
ADSP-21xxr
Type
Fixed Pointr
Datasheet
1.ADSP-2184LBSTZ-160.pdf
(48 pages)
Specifications of ADSP-2187LBSTZ-210
Interface
Host Interface, Serial Port
Clock Rate
52MHz
Non-volatile Memory
External
On-chip Ram
160kB
Voltage - I/o
3.30V
Voltage - Core
3.30V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ADSP-2187LBSTZ210
ADSP-2187LBSTZ210
ADSP-2187LBSTZ210
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADSP-2187LBSTZ-210
Manufacturer:
ANALOG
Quantity:
45
Company:
Part Number:
ADSP-2187LBSTZ-210
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
ADSP-2187LBSTZ-210
Manufacturer:
ADI/亚德诺
Quantity:
20 000
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L
LQFP PACKAGE PINOUT
The LQFP package pinout is shown in
bold text in the table replace the plain-text-named functions
when Mode C equals 1. A plus sign (+) separates two functions
when either function can be active for either major I/O mode.
Signals enclosed in brackets are state bits latched from the value
Table 29. LQFP Pin Assignments
1
Lead No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Mode D function available on ADSP-2187L only.
Lead Name
A4/IAD3
A5/IAD4
GND
A6/IAD5
A7/IAD6
A8/IAD7
A9/IAD8
A10/IAD9
A11/IAD10
A12/IAD11
A13/IAD12
GND
CLKIN
XTAL
V
CLKOUT
GND
V
WR
RD
BMS
DMS
PMS
IOMS
CMS
DDEXT
DDINT
Lead No.
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Table
29. Pin names in
Lead Name
IRQE + PF4
IRQL0 + PF5
GND
IRQL1 + PF6
IRQ2 + PF7
DT0
TFS0
RFS0
DR0
SCLK0
V
DT1/FO
TFS1/IRQ1
RFS1/IRQ0
DR1/FI
GND
SCLK1
ERESET
RESET
EMS
EE
ECLK
ELOUT
ELIN
EINT
DDEXT
Rev. C | Page 44 of 48 | January 2008
Lead No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
of the pin at the deassertion of RESET. The multiplexed pins
DT1/FO, TFS1/IRQ1, RFS1/IRQ0, and DR1/FI, are mode
selectable by setting Bit 10 (SPORT1 configure) of the System
Control Register. If Bit 10 = 1, these pins have serial port func-
tionality. If Bit 10 = 0, these pins are the external interrupt and
flag pins. This bit is set to 1 by default, upon reset.
Lead Name
EBR
BR
EBG
BG
D0/IAD13
D1/IAD14
D2/IAD15
D3/IACK
V
GND
D4/IS
D5/IAL
D6/IRD
D7/IWR
D8
GND
V
D9
D10
D11
GND
D12
D13
D14
D15
DDINT
DDEXT
Lead No.
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Lead Name
D16
D17
D18
D19
GND
D20
D21
D22
D23
FL2
FL1
FL0
PF3 [Mode D
PF2 [Mode C]
V
PWD
GND
PF1 [Mode B]
PF0 [Mode A]
BGH
PWDACK
A0
A1/IAD0
A2/IAD1
A3/IAD2
DDEXT
1
]