ADSP-2191MBSTZ-140 Analog Devices Inc, ADSP-2191MBSTZ-140 Datasheet - Page 37

• Manufacturer Part Number: ADSP-2191MBSTZ-140
• Description: IC,DSP,16-BIT,CMOS,QFP,144PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: ADSP-21xxr
• Type: Fixed Pointr

Specifications of ADSP-2191MBSTZ-140

• Interface: Host Interface, SPI, SSP, UART
• Clock Rate: 140MHz
• Non-volatile Memory: External
• On-chip Ram: 160kB
• Voltage - I/o: 3.00V, 3.30V
• Voltage - Core: 2.50V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 16b
• Clock Freq (max): 140MHz
• Mips: 140
• Device Input Clock Speed: 140MHz
• Ram Size: 160KB
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (min): 2.37/2.97V
• Operating Supply Voltage (max): 2.63/3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADSP-2191MBSTZ140

Serial Peripheral Interface (SPI) Port—Master Timing
Table 20
Table 20. Serial Peripheral Interface (SPI) Port—Master Timing
REV. 0
Parameter
Switching Characteristics
t
t
t
t
t
t
t
t
Timing Requirements
t
t
SDSCIM
SPICHM
SPICLM
SPICLK
HDSM
SPITDM
DDSPID
HDSPID
SSPID
HSPID
and
CPHA = 1
CPHA = 0
(C P OL = 1 )
(x = 0 or 1 )
(C P O L = 0 )
(O U TP U T )
( OU T PU T)
(O U TP U T )
( OU T PU T )
( OU TP U T)
Figure 21
(IN P U T)
SPIxSEL
(IN PU T )
SC L K
SC LK
MIS O
SPIxSEL Low to First SCLK edge (x=0 or 1)
Serial Clock High Period
Serial Clock Low Period
Serial Clock Period
Last SCLK Edge to SPIxSEL High (x=0 or 1)
Sequential Transfer Delay
SCLK Edge to Data Output Valid (Data Out Delay)
SCLK Edge to Data Output Invalid (Data Out Hold)
Data Input Valid to SCLK Edge (Data Input Setup)
SCLK Sampling Edge to Data Input Invalid (Data In Hold)
M IS O
M OS I
M O S I
t
describe SPI port master operations.
S S P I D
t
t
S D S C I M
S P I C L M
t
V A L ID
S S P I D
M S B
Figure 21. Serial Peripheral Interface (SPI) Port—Master Timing
t
S P I C H M
MS B
V A LID
t
M S B
H S P I D
t
S P I C L M
t
D D S P I D
M S B
t
H S P I D
t
D D S P I D
t
S P I C H M
–37–
t
H D S P I D
V A LID
t
t
LS B
S P I C L K
S S P I D
t
H D S P I D
L S B
V A LID
LS B
Min
2t
2t
2t
4t
2t
2t
0
0
8
1
HCLK
HCLK
HCLK
HCLK
HCLK
HCLK
t
H D S M
LS B
t
–3
–3
–3
–1
–3
–2
H S P I D
t
S P I T D M
ADSP-2191M
Max
6
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns