ADSP-BF512KSWZ-3 Analog Devices Inc, ADSP-BF512KSWZ-3 Datasheet - Page 8

• Manufacturer Part Number: ADSP-BF512KSWZ-3
• Description: Low-Power Blackfin Processor
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF512KSWZ-3

• Interface: I²C, PPI, SPI, SPORT, UART/USART
• Clock Rate: 300MHz
• Non-volatile Memory: External
• On-chip Ram: 116kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.30V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 176-LQFP Exposed Pad, 176-eLQFP, 176-HLQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
The stopwatch function counts down from a programmed
value, with one-second resolution. When the stopwatch is
enabled and the counter underflows, an interrupt is generated.
Like the other peripherals, the RTC can wake up the processor
from sleep mode upon generation of any RTC wakeup event.
Additionally, an RTC wakeup event can wake up the processor
from deep sleep mode or cause a transition from the hibernate
state.
Connect RTC signals RTXI and RTXO with external compo-
nents as shown in
Watchdog Timer
The ADSP-BF51x processors include a 32-bit timer that can be
used to implement a software watchdog function. A software
watchdog can improve system availability by forcing the proces-
sor to a known state through generation of a hardware reset,
nonmaskable interrupt (NMI), or general-purpose interrupt, if
the timer expires before being reset by software. The program-
mer initializes the count value of the timer, enables the
appropriate interrupt, then enables the timer. Thereafter, the
software must reload the counter before it counts to zero from
the programmed value. This protects the system from remain-
ing in an unknown state where software, which would normally
reset the timer, has stopped running due to an external noise
condition or software error.
If configured to generate a hardware reset, the watchdog timer
resets both the core and the processor peripherals. After a reset,
software can determine if the watchdog was the source of the
hardware reset by interrogating a status bit in the watchdog
timer control register.
The timer is clocked by the system clock (SCLK) at a maximum
frequency of f
Timers
There are nine general-purpose programmable timer units in
the ADSP-BF51x processors. Eight timers have an external sig-
nal that can be configured either as a pulse width modulator
(PWM) or timer output, as an input to clock the timer, or as a
SUGGESTED COMPONENTS:
X1 = ECLIPTEK EC38J (THROUGH-HOLE PACKAGE) OR
C1 = 22 pF
C2 = 22 pF
R1 = 10 M:
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2
SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 pF.
EPSON MC405 12 pF LOAD (SURFACE-MOUNT PACKAGE)
C1
RTXI
SCLK
Figure 3. External Components for RTC
.
Figure
R1
X1
3.
C2
RTXO
Rev. B | Page 8 of 68 | January 2011
mechanism for measuring pulse widths and periods of external
events. These timers can be synchronized to an external clock
input to the several other associated PF signals, an external
clock input to the PPI_CLK input signal, or to the internal
SCLK.
The timer units can be used in conjunction with the two UARTs
to measure the width of the pulses in the data stream to provide
a software auto-baud detect function for the respective serial
channels.
The timers can generate interrupts to the processor core provid-
ing periodic events for synchronization, either to the system
clock or to a count of external signals.
In addition to the eight general-purpose programmable timers,
a ninth timer is also provided. This extra timer is clocked by the
internal processor clock and is typically used as a system tick
clock for generation of operating system periodic interrupts.
3-Phase PWM
The processors integrate a flexible and programmable 3-phase
PWM waveform generator that can be programmed to generate
the required switching patterns to drive a 3-phase voltage
source inverter for ac induction (ACIM) or permanent magnet
synchronous (PMSM) motor control. In addition, the PWM
block contains special functions that considerably simplify the
generation of the required PWM switching patterns for control
of the electronically commutated motor (ECM) or brushless dc
motor (BDCM). Software can enable a special mode for
switched reluctance motors (SRM).
Features of the 3-phase PWM generation unit are:
General-Purpose (GP) Counter
A 32-bit GP counter is provided that can sense 2-bit quadrature
or binary codes as typically emitted by industrial drives or man-
ual thumb wheels. The counter can also operate in general-
purpose up/down count modes. Then, count direction is either
controlled by a level-sensitive input signal or by two edge
detectors.
• 16-bit center-based PWM generation unit
• Programmable PWM pulse width
• Single/double update modes
• Programmable dead time and switching frequency
• Twos-complement implementation which permits smooth
• Possibility to synchronize the PWM generation to an exter-
• Special provisions for BDCM operation (crossover and
• Wide variety of special switched reluctance (SR) operating
• Output polarity and clock gating control
• Dedicated asynchronous PWM shutdown signal
transition to full ON and full OFF states
nal synchronization
output enable functions)
modes