ADSP-BF527KBCZ-6 Analog Devices Inc, ADSP-BF527KBCZ-6 Datasheet - Page 14

ADSP-BF527 Processor,600Mhz,Ethernet,USB

ADSP-BF527KBCZ-6

Manufacturer Part Number
ADSP-BF527KBCZ-6
Description
ADSP-BF527 Processor,600Mhz,Ethernet,USB
Manufacturer
Analog Devices Inc
Series
Blackfin®r
Type
Fixed Pointr

Specifications of ADSP-BF527KBCZ-6

Interface
DMA, Ethernet, I²C, PPI, SPI, SPORT, UART, USB
Clock Rate
600MHz
Non-volatile Memory
ROM (32 kB)
On-chip Ram
132kB
Voltage - I/o
1.8V, 2.5V, 3.3V
Voltage - Core
1.10V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
289-CSPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
ADZS-BF527-MPSKIT - BOARD EVAL MEDIA PLAYER BF527ADZS-BF527-EZLITE - BOARD EVAL ADSP-BF527
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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synchronization to Field 1. Data is transferred to or from the
synchronous channels through eight DMA engines that work
autonomously from the processor core.
USB ON-THE-GO DUAL-ROLE DEVICE CONTROLLER
The USB OTG dual-role device controller (USBDRC) provides
a low-cost connectivity solution for consumer mobile devices
such as cell phones, digital still cameras, and MP3 players,
allowing these devices to transfer data using a point-to-point
USB connection without the need for a PC host. The USBDRC
module can operate in a traditional USB peripheral-only mode
as well as the host mode presented in the On-the-Go (OTG)
supplement to the USB 2.0 specification. In host mode, the USB
module supports transfers at high speed (480 Mbps), full speed
(12 Mbps), and low speed (1.5 Mbps) rates. Peripheral-only
mode supports the high- and full-speed transfer rates.
The USB clock (USB_XI) is provided through a dedicated exter-
nal crystal or crystal oscillator. See
On-The-Go—Receive and Transmit Timing on Page 59
related timing requirements. If using a crystal to provide the
USB clock, use a parallel-resonant, fundamental mode, micro-
processor-grade crystal.
The USB on-the-go dual-role device controller includes a phase
locked loop with programmable multipliers to generate the nec-
essary internal clocking frequency for USB. The multiplier value
should be programmed based on the USB_XI frequency to
achieve the necessary 480 MHz internal clock for USB high
speed operation. For example, for a USB_XI crystal frequency of
24 MHz, the USB_PLLOSC_CTRL register should be pro-
grammed with a multiplier value of 20 to generate a 480 MHz
internal clock.
CODE SECURITY WITH LOCKBOX SECURE
TECHNOLOGY
A security system consisting of a blend of hardware and soft-
ware provides customers with a flexible and rich set of code
security features with Lockbox
tures include:
The security scheme is based upon the concept of authentica-
tion of digital signatures using standards-based algorithms and
provides a secure processing environment in which to execute
code and protect assets. See
claimer on Page
DYNAMIC POWER MANAGEMENT
The processor provides five operating modes, each with a differ-
ent performance/power profile. In addition, dynamic power
management provides the control functions to dynamically alter
the processor core supply voltage, further reducing power dissi-
pation. When configured for a 0 V core supply voltage, the
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
• OTP memory
• Unique chip ID
• Code authentication
• Secure mode of operation
21.
Lockbox Secure Technology Dis-
TM
Secure Technology. Key fea-
Universal Serial Bus (USB)
Rev. B | Page 14 of 88 | May 2010
for
processor enters the hibernate state. Control of clocking to each
of the processor peripherals also reduces power consumption.
See
Table 4. Power Settings
Full-On Operating Mode—Maximum Performance
In the full-on mode, the PLL is enabled and is not bypassed,
providing capability for maximum operational frequency. This
is the power-up default execution state in which maximum per-
formance can be achieved. The processor core and all enabled
peripherals run at full speed.
Active Operating Mode—Moderate Dynamic Power
Savings
In the active mode, the PLL is enabled but bypassed. Because the
PLL is bypassed, the processor’s core clock (CCLK) and system
clock (SCLK) run at the input clock (CLKIN) frequency. DMA
access is available to appropriately configured L1 memories.
In the active mode, it is possible to disable the control input to
the PLL by setting the PLL_OFF bit in the PLL control register.
This register can be accessed with a user-callable routine in the
on-chip ROM called bfrom_SysControl(). If disabled, the PLL
control input must be re-enabled before transitioning to the
full-on or sleep modes.
For more information about PLL controls, see the “Dynamic
Power Management” chapter in the ADSP-BF52x Blackfin Pro-
cessor Hardware Reference.
Sleep Operating Mode—High Dynamic Power Savings
The sleep mode reduces dynamic power dissipation by disabling
the clock to the processor core (CCLK). The PLL and system
clock (SCLK), however, continue to operate in this mode. Typi-
cally, an external event or RTC activity wakes up the processor.
When in the sleep mode, asserting a wakeup enabled in the
SIC_IWRx registers causes the processor to sense the value of
the BYPASS bit in the PLL control register (PLL_CTL). If
BYPASS is disabled, the processor transitions to the full-on
mode. If BYPASS is enabled, the processor transitions to the
active mode.
System DMA access to L1 memory is not supported in
sleep mode.
Mode/State PLL
Full-On
Active
Sleep
Deep Sleep
Hibernate
Table 4
for a summary of the power settings for each mode.
Enabled No
Enabled/
Disabled
Enabled —
Disabled —
Disabled —
PLL
Bypassed
Yes
Core
Clock
(CCLK)
Enabled Enabled On
Enabled Enabled On
Disabled Enabled On
Disabled Disabled On
Disabled Disabled Off
System
Clock
(SCLK)
Core
Power

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