ADSP-BF527KBCZ-6 Analog Devices Inc, ADSP-BF527KBCZ-6 Datasheet - Page 49

• Manufacturer Part Number: ADSP-BF527KBCZ-6
• Description: ADSP-BF527 Processor,600Mhz,Ethernet,USB
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF527KBCZ-6

• Interface: DMA, Ethernet, I²C, PPI, SPI, SPORT, UART, USB
• Clock Rate: 600MHz
• Non-volatile Memory: ROM (32 kB)
• On-chip Ram: 132kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.10V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 289-CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ADZS-BF527-MPSKIT - BOARD EVAL MEDIA PLAYER BF527ADZS-BF527-EZLITE - BOARD EVAL ADSP-BF527
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Parallel Peripheral Interface Timing
Table 40
Figure 27 on Page 56
operations.
Table 40. Parallel Peripheral Interface Timing for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors
1
Table 41. Parallel Peripheral Interface Timing for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors
1
Parameter
Timing Requirements
t
t
Timing Requirements - GP Input and Frame Capture Modes
t
t
t
t
Switching Characteristics - GP Output and Frame Capture Modes
t
t
t
t
Parameter
Timing Requirements
t
t
Timing Requirements - GP Input and Frame Capture Modes
t
t
t
t
Switching Characteristics - GP Output and Frame Capture Modes
t
t
t
t
PPI_CLK frequency cannot exceed f
PPI_CLK frequency cannot exceed f
PCLKW
PCLK
SFSPE
HFSPE
SDRPE
HDRPE
DFSPE
HOFSPE
DDTPE
HDTPE
PCLKW
PCLK
SFSPE
HFSPE
SDRPE
HDRPE
DFSPE
HOFSPE
DDTPE
HDTPE
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
and
Figure 20 on Page
PPI_CLK Width
PPI_CLK Period
External Frame Sync Setup Before PPI_CLK
(Nonsampling Edge for Rx, Sampling Edge for Tx)
External Frame Sync Hold After PPI_CLK
Receive Data Setup Before PPI_CLK
Receive Data Hold After PPI_CLK
Internal Frame Sync Delay After PPI_CLK
Internal Frame Sync Hold After PPI_CLK
Transmit Data Delay After PPI_CLK
Transmit Data Hold After PPI_CLK
describe parallel peripheral interface
PPI_CLK Width
PPI_CLK Period
External Frame Sync Setup Before PPI_CLK
(Nonsampling Edge for Rx, Sampling Edge for Tx)
External Frame Sync Hold After PPI_CLK
Receive Data Setup Before PPI_CLK
Receive Data Hold After PPI_CLK
Internal Frame Sync Delay After PPI_CLK
Internal Frame Sync Hold After PPI_CLK
Transmit Data Delay After PPI_CLK
Transmit Data Hold After PPI_CLK
SCLK
SCLK
50,
/2
/2
1
1
Figure 24 on Page
1
1
Rev. B | Page 49 of 88 | May 2010
54, and
Min
6.0
20.0
6.7
1.0
3.5
2.0
1.7
2.3
1.8V Nominal
V
DDEXT
Min
6.4
25.0
6.7
1.2
4.1
2.0
1.7
2.3
Max
8.0
8.0
1.8V Nominal
V
DDEXT
Max
8.0
8.2
1.6
Min
6.0
15.0
6.7
1.0
3.5
1.7
1.9
2.5/3.3V Nominal
Min
6.4
20.0
6.7
1.2
3.5
1.6
1.7
1.9
2.5/3.3V Nominal
V
DDEXT
Max
8.0
8.0
V
DDEXT
Max
8.0
8.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns