ADUC7021BCPZ62-RL Analog Devices Inc, ADUC7021BCPZ62-RL Datasheet - Page 12

• Manufacturer Part Number: ADUC7021BCPZ62-RL
• Description: IC,MICROCONTROLLER,16-BIT,ARM7 CPU,CMOS,LLCC,40PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7021BCPZ62-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 44MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: PLA, PWM, PSM, Temp Sensor, WDT
• Number Of I /o: 13
• Program Memory Size: 62KB (62K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7019/20/21/22/24/25/26/27/28/29
Table 6. SPI Master Mode Timing (Phase Mode = 1)
Parameter
t
t
t
t
t
t
t
t
t
1
2
SL
SH
DAV
DSU
DHD
DF
DR
SR
SF
t
t
HCLK
UCLK
depends on the clock divider or CD bits in the PLLCON MMR. t
= 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider; see Figure 57.
(POLARITY = 0)
(POLARITY = 1)
Description
SCLOCK low pulse width
SCLOCK high pulse width
Data output valid after SCLOCK edge
Data input setup time before SCLOCK edge
Data input hold time after SCLOCK edge
Data output fall time
Data output rise time
SCLOCK rise time
SCLOCK fall time
SCLOCK
SCLOCK
MOSI
MISO
1
t
1
DAV
t
SH
Figure 6. SPI Master Mode Timing (Phase Mode = 1)
t
DSU
MSB IN
HCLK
t
DHD
2
MSB
= t
t
SL
Rev. C | Page 12 of 96
2
UCLK
/2
t
DF
CD
; see Figure 57.
t
DR
BITS 6 TO 1
BITS 6 TO 1
Min
1 × t
2 × t
UCLK
UCLK
t
SR
Typ
(SPIDIV + 1) × t
(SPIDIV + 1) × t
5
5
5
5
LSB IN
t
SF
LSB
HCLK
HCLK
Max
25
12.5
12.5
12.5
12.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns