ADUC7021BCPZ62-RL Analog Devices Inc, ADUC7021BCPZ62-RL Datasheet - Page 56
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ADUC7021BCPZ62-RL
Manufacturer Part Number
ADUC7021BCPZ62-RL
Description
IC,MICROCONTROLLER,16-BIT,ARM7 CPU,CMOS,LLCC,40PIN,PLASTIC
Manufacturer
Analog Devices Inc
Series
MicroConverter® ADuC7xxxr
Datasheet
1.USB-I2CLIN-CONV-Z.pdf
(96 pages)
Specifications of ADUC7021BCPZ62-RL
Core Processor
ARM7
Core Size
16/32-Bit
Speed
44MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
PLA, PWM, PSM, Temp Sensor, WDT
Number Of I /o
13
Program Memory Size
62KB (62K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
40-LFCSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
ADuC7019/20/21/22/24/25/26/27/28/29
MMRs and Keys
The operating mode, clocking mode, and programmable clock
divider are controlled via two MMRs: PLLCON (see Table 61)
and POWCON (see Table 64). PLLCON controls the operating
mode of the clock system, whereas POWCON controls the core
clock frequency and the power-down mode.
To prevent accidental programming, a certain sequence (see
Table 65) must be followed to write to the PLLCON and
POWCON registers.
Table 59. PLLKEYx Registers
Name
PLLKEY1
PLLKEY2
Table 60. PLLCON Register
Name
PLLCON
Table 61. PLLCON MMR Bit Designations
Bit
7:6
5
4:2
1:0
Table 62. POWKEYx Registers
Name
POWKEY1
POWKEY2
Name
OSEL
MDCLK
Address
0xFFFF0410
0xFFFF0418
Address
0xFFFF0414
Address
0xFFFF0404
0xFFFF040C
Value
00
01
10
11
Description
Reserved.
32 kHz PLL input selection. Set by
user to select the internal 32 kHz
oscillator. Set by default. Cleared by
user to select the external 32 kHz crystal.
Reserved.
Clocking modes.
Reserved.
PLL. Default configuration.
Reserved.
External clock on the P0.7 pin.
Default Value
0x0000
0x0000
Default Value
0x21
Default Value
0x0000
0x0000
Access
W
W
Access
R/W
Access
W
W
Rev. C | Page 56 of 96
Table 63. POWCON Register
Name
POWCON
Table 64. POWCON MMR Bit Designations
Bit
7
6:4
3
2:0
Table 65. PLLCON and POWCON Write Sequence
PLLCON
PLLKEY1 = 0xAA
PLLCON = 0x01
PLLKEY2 = 0x55
Name
PC
CD
Address
0xFFFF0408
Value
000
001
010
011
100
Others
000
001
010
011
100
101
110
111
Operating modes.
Description
Reserved.
Active mode.
Pause mode.
Nap.
Sleep mode. IRQ0 to IRQ3 and Timer2
can wake up the part.
Stop mode. IRQ0 to IRQ3 can wake up
the part.
Reserved.
Reserved.
CPU clock divider bits.
41.78 MHz.
20.89 MHz.
10.44 MHz.
5.22 MHz.
2.61 MHz.
1.31 MHz.
653 kHz.
326 kHz.
Default Value
0x0003
POWCON
POWKEY1 = 0x01
POWCON = user value
POWKEY2 = 0xF4
Access
R/W