ADUC7124BCPZ126-RL Analog Devices Inc, ADUC7124BCPZ126-RL Datasheet - Page 62

• Manufacturer Part Number: ADUC7124BCPZ126-RL
• Description: ARM7 With 12-Bit ADC & DACs, 128kB Flash
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7124BCPZ126-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 41.78MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 126KB (63K x 16)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 10x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7124/ADuC7126
COM1DIV0 Register
Name:
Address:
Default Value:
Access:
COM1DIV0 is a low byte divisor latch for UART1. COM1TX,
COM1RX, and COM1DIV0 share the same address location.
COM1TX and COM1RX can be accessed when Bit 7 in
COM1CON0 register is cleared. COM1DIV0 can be accessed
when Bit 7 of COM1CON0 is set.
COM0IEN0 Register
Name:
Address:
Default Value:
Access:
COM0IEN0 is the interrupt enable register for UART0.
COM1IEN0 Register
Name:
Address:
Default Value:
Access:
COM1IEN0 is the interrupt enable register for UART1.
Table 92. COMxIEN0 MMR Bit Descriptions
Bit
[7:4]
3
2
1
0
Name
EDSSI
ELSI
ETBEI
ERBFI
Description
Reserved.
Modem status interrupt enable bit.
Set by the user to enable generation of an
interrupt if any of COMXSTA1[3:1] are set.
Cleared by the user.
Rx status interrupt enable bit.
Set by the user to enable generation of an
interrupt if any of COMxSTA0[3:0] are set.
Cleared by the user.
Enable transmit buffer empty interrupt.
Set by the user to enable interrupt when the
buffer is empty during a transmission.
Cleared by the user.
Enable receive buffer full interrupt.
In non-FIFO mode, set by the user to enable
an interrupt when buffer is full during a
reception. Cleared by the user.
In FIFO mode, set by the user to enable an
interrupt when trigger level is reached. It also
controls the character receive timeout
interrupt. Cleared by the user.
COM1DIV0
0xFFFF0740
0x00
Read/write
COM0IEN0
0xFFFF0704
0x00
Read/write
COM1IEN0
0xFFFF0744
0x00
Read/write
Rev. B | Page 62 of 104
COM0DIV1 Register
Name:
Address:
Default Value:
Access:
COM0DIV1 is a divisor latch (high byte) register for UART0.
COM1DIV1 Register
Name:
Address:
Default Value:
Access:
COM1DIV1 is a divisor latch (high byte) register for UART1.
COM0IID0 Register
Name:
Address:
Default Value:
Access:
COM0IID0 is the interrupt identification register for UART0. It
also indicates if the UART is in FIFO mode.
COM1IID0 Register
Name:
Address:
Default Value:
Access:
COM1IID0 is the interrupt identification register for UART1. It
also indicates if the UART is in FIFO mode.
COM0DIV1
0xFFFF0704
0x00
Read/write
COM1DIV1
0xFFFF0744
0x00
Read/write
COM0IID0
0xFFFF0708
0x01
Read only
COM1IID0
0xFFFF0748
0x01
Read only