ADUC7124BCPZ126-RL Analog Devices Inc, ADUC7124BCPZ126-RL Datasheet - Page 83

• Manufacturer Part Number: ADUC7124BCPZ126-RL
• Description: ARM7 With 12-Bit ADC & DACs, 128kB Flash
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7124BCPZ126-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 41.78MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 126KB (63K x 16)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 10x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PLAADC Register
Name:
Address:
Default Value:
Access:
PLAADC is the PLA source for the ADC start conversion signal.
Table 123. PLAADC MMR Bit Descriptions
Bit
[31:5]
4
[3:0]
PLADIN Register
Name:
Address:
Default Value:
Access:
PLADIN is a data input MMR for PLA.
Value
0000
0001
1111
Description
Reserved.
ADC start conversion enable bit.
Set by the user to enable ADC start
conversion from PLA.
Cleared by the user to disable ADC start
conversion from PLA.
ADC start conversion source.
PLA Element 0.
PLA Element 1.
PLA Element 15.
PLAADC
0xFFFF0B48
0x00000000
Read/write
PLADIN
0xFFFF0B4C
0x00000000
Read/write
Rev. B | Page 83 of 104
Table 124. PLADIN MMR Bit Descriptions
Bit
[31:16]
[15:0]
PLADOUT Register
Name:
Address:
Default Value:
Access:
PLADOUT is a data output MMR for PLA. This register is
always updated.
Table 125. PLADOUT MMR Bit Descriptions
Bit
[31:16]
[15:0]
PLALCK Register
Name:
Address:
Default Value:
Access:
PLALCK is a PLA lock option. Bit 0 is written only once. When
set, it does not allow modification of any of the PLA MMRs,
except PLADIN. A PLA tool is provided in the development
system to easily configure the PLA.
Description
Reserved.
Output bit from Element 15 to Element 0.
Description
Reserved.
Input bit to Element 15 to Element 0.
PLADOUT
0xFFFF0B50
0x00000000
Read only
PLALCK
0xFFFF0B54
0x00
Write only
ADuC7124/ADuC7126