ADUC824BSZ Analog Devices Inc, ADUC824BSZ Datasheet - Page 13

• Manufacturer Part Number: ADUC824BSZ
• Description: IC,Data Acquisition CODEC,2-CHANNEL,QFP,52PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC8xxr

Specifications of ADUC824BSZ

• Core Processor: 8052
• Core Size: 8-Bit
• Speed: 12.58MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 34
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 640 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.25 V
• Data Converters: A/D 3x16b, 4x24b; D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-MQFP, 52-PQFP
• Cpu Family: ADuC8xx
• Device Core: 8052
• Device Core Size: 8b
• Frequency (max): 12.58MHz
• Interface Type: I2C/SPI/UART
• Total Internal Ram Size: 256Byte
• # I/os (max): 26
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 2(2-chx24-bit)
• On-chip Dac: 1-chx12-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 52
• Package Type: MQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Parameter
I
2
Input filtering on both the SCLOCK and SDATA inputs suppresses noise spikes less than 50 ns.
C-COMPATIBLE INTERFACE TIMING
t
t
t
t
t
t
t
t
t
t
t
L
H
SHD
DSU
DHD
RSU
PSU
BUF
R
F
SUP
SDATA (I/O)
SCLK (I)
SCLOCK Low Pulsewidth
SCLOCK High Pulsewidth
Start Condition Hold Time
Data Setup Time
Data Hold Time
Setup Time for Repeated Start
Stop Condition Setup Time
Bus Free Time between a STOP
Condition and a START Condition
Rise Time of Both SCLOCK and SDATA
Fall Time of Both SCLOCK and SDATA
Pulsewidth of Spike Suppressed
t
PSU
CONDITION
STOP
PS
t
BUF
CONDITION
START
t
DSU
t
SHD
MSB
1
t
DHD
2-7
t
L
Min
4.7
4.0
0.6
100
0.6
0.6
1.3
LSB
8
t
SUP
t
SUP
t
H
t
DSU
ACK
Max
0.9
300
300
50
9
t
RSU
t
DHD
REPEATED
START
S(R)
Unit
µs
µs
µs
µs
µs
µs
µs
µs
ns
ns
ns
t
F
MSB
t
t
1
F
R
t
R
ADuC824
Figure
7
7
7
7
7
7
7
7
7
7
7